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target/arm: Move initialization of debug ID registers 

Move the initialization of the debug ID registers to aa32_max_features,
which is used to set the 32-bit ID registers. This ensures that the
debug ID registers are consistently set for the max CPU in a single
place.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240624180915.4528-3-gustavo.romero@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Gustavo Romero 2024-06-24 18:09:14 +00:00 committed by Peter Maydell
parent 4df378ab51
commit c5f9e8bb93
2 changed files with 30 additions and 3 deletions
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2
target/arm/cpu.h
View File

@ -2299,6 +2299,8 @@ FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
FIELD(DBGDEVID, AUXREGS, 24, 4)
FIELD(DBGDEVID, CIDMASK, 28, 4)
FIELD(DBGDEVID1, PCSROFFSET, 0, 4)
FIELD(MVFR0, SIMDREG, 0, 4)
FIELD(MVFR0, FPSP, 4, 4)
FIELD(MVFR0, FPDP, 8, 4)

31
target/arm/tcg/cpu32.c
View File

@ -87,6 +87,34 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
cpu->isar.id_dfr0 = t;
/* Debug ID registers. */
/* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
t = 0x00008000;
t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */
t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
cpu->isar.dbgdidr = t;
t = 0;
t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
cpu->isar.dbgdevid = t;
/* Bits[31:4] are RES0. */
t = 0;
t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
cpu->isar.dbgdevid1 = t;
t = cpu->isar.id_dfr1;
t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
cpu->isar.id_dfr1 = t;
@ -955,9 +983,6 @@ static void arm_max_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x00110f13;
cpu->isar.dbgdevid1 = 0x2;
cpu->isar.reset_pmcr_el0 = 0x41013000;
cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */