From c5b4ee5bb799685e1c5a4a30ab40013a984daded Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Sat, 11 Sep 2021 16:00:01 +0200 Subject: [PATCH] target/riscv: Introduce temporary in gen_add_uw() Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*") Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b72e76255c..c0a6e25826 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3) static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) { - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_add_tl(ret, arg1, arg2); + TCGv t = tcg_temp_new(); + tcg_gen_ext32u_tl(t, arg1); + tcg_gen_add_tl(ret, t, arg2); + tcg_temp_free(t); } static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)