From b0d9ffcd0251161c7c92f94804dcf599dfa3edeb Mon Sep 17 00:00:00 2001 From: Michael Contreras Date: Sun, 2 Dec 2012 20:11:22 -0800 Subject: [PATCH 1/8] e1000: Discard packets that are too long if !SBP and !LPE The e1000_receive function for the e1000 needs to discard packets longer than 1522 bytes if the SBP and LPE flags are disabled. The linux driver assumes this behavior and allocates memory based on this assumption. Signed-off-by: Michael Contreras Signed-off-by: Anthony Liguori --- hw/e1000.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/e1000.c b/hw/e1000.c index cb7e7e8366..5537ad2fc4 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -59,6 +59,9 @@ static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); #define PNPMMIO_SIZE 0x20000 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */ +/* this is the size past which hardware will drop packets when setting LPE=0 */ +#define MAXIMUM_ETHERNET_VLAN_SIZE 1522 + /* * HW models: * E1000_DEV_ID_82540EM works with Windows and Linux @@ -805,6 +808,13 @@ e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size) size = sizeof(min_buf); } + /* Discard oversized packets if !LPE and !SBP. */ + if (size > MAXIMUM_ETHERNET_VLAN_SIZE + && !(s->mac_reg[RCTL] & E1000_RCTL_LPE) + && !(s->mac_reg[RCTL] & E1000_RCTL_SBP)) { + return size; + } + if (!receive_filter(s, buf, size)) return size; From 6d6c9f59ca1b1a76ade7ad868bef191818f58819 Mon Sep 17 00:00:00 2001 From: Anthony Liguori Date: Mon, 3 Dec 2012 08:02:50 -0600 Subject: [PATCH 2/8] Update version for 1.3.0 release Signed-off-by: Anthony Liguori --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 19838b230d..f0bb29e763 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.92 +1.3.0 From 16c6c80ac3a772b42a87b77dfdf0fdac7c607b0e Mon Sep 17 00:00:00 2001 From: Anthony Liguori Date: Mon, 3 Dec 2012 14:08:40 -0600 Subject: [PATCH 3/8] Open up 1.4 development branch Signed-off-by: Anthony Liguori --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index f0bb29e763..52356d37e0 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.3.0 +1.3.50 From d4d230da08918183929c7d6cb54824b391536904 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Wed, 5 Dec 2012 16:53:42 +1000 Subject: [PATCH 4/8] xilinx_axienet: Implement R_IS behaviour The interrupt status register R_IS is the standard clear-on-write behaviour. This was unimplemented and defaulting to updating the register to the written value. Implemented clear-on-write. Reported-by: Jason Wu Signed-off-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- hw/xilinx_axienet.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c index baae02bd66..f2e3bf1274 100644 --- a/hw/xilinx_axienet.c +++ b/hw/xilinx_axienet.c @@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr, s->maddr[s->fmi & 3][addr & 1] = value; break; + case R_IS: + s->regs[addr] &= ~value; + break; + case 0x8000 ... 0x83ff: s->ext_mtable[addr - 0x8000] = value; break; From 859cc10d23e619153670fc58683373fa24d25b68 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Wed, 5 Dec 2012 16:53:43 +1000 Subject: [PATCH 5/8] xilinx_uartlite: suppress "cannot receive message" This message is not an error condition, its just informing the user that the device is corking the uart traffic to not drop characters. Reported-by: Jason Wu Signed-off-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- hw/xilinx_uartlite.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c index d20fc4124b..f890f2363d 100644 --- a/hw/xilinx_uartlite.c +++ b/hw/xilinx_uartlite.c @@ -182,12 +182,8 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) static int uart_can_rx(void *opaque) { struct xlx_uartlite *s = opaque; - int r; - r = s->rx_fifo_len < sizeof(s->rx_fifo); - if (!r) - printf("cannot receive!\n"); - return r; + return s->rx_fifo_len < sizeof(s->rx_fifo); } static void uart_event(void *opaque, int event) From 80625b97b52836b944a6438e8e3e9d992e6a00b6 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Wed, 5 Dec 2012 16:53:44 +1000 Subject: [PATCH 6/8] xilinx_uartlite: Accept input after rx FIFO pop The device return false from the can receive function when the FIFO is full. This mean the device should check for buffered input whenever a byte is popped from the FIFO. Reported-by: Jason Wu Signed-off-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- hw/xilinx_uartlite.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c index f890f2363d..02c5850331 100644 --- a/hw/xilinx_uartlite.c +++ b/hw/xilinx_uartlite.c @@ -97,6 +97,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) s->rx_fifo_len--; uart_update_status(s); uart_update_irq(s); + qemu_chr_accept_input(s->chr); break; default: From 34f5606ee101f82a247d09d05644ad2a63c8e342 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Mon, 26 Nov 2012 16:13:21 +0100 Subject: [PATCH 7/8] target-mips: Fix incorrect code and test for INSV Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic Reviewed-by: Eric Johnson Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 2 +- tests/tcg/mips/mips32-dsp/insv.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index e7949c22c0..fda5f0460b 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ \ filter = ((int32_t)0x01 << size) - 1; \ filter = filter << pos; \ - temprs = rs & filter; \ + temprs = (rs << pos) & filter; \ temprt = rt & ~filter; \ temp = temprs | temprt; \ \ diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c index 7e3b047606..243b00733d 100644 --- a/tests/tcg/mips/mips32-dsp/insv.c +++ b/tests/tcg/mips/mips32-dsp/insv.c @@ -10,7 +10,7 @@ int main() dsp = 0x305; rt = 0x12345678; rs = 0x87654321; - result = 0x12345338; + result = 0x12345438; __asm ("wrdsp %2, 0x03\n\t" "insv %0, %1\n\t" From 19e6c50d2d843220efbdd3b2db21d83c122c364a Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Wed, 5 Dec 2012 00:29:10 +0100 Subject: [PATCH 8/8] target-mips: Fix incorrect shift for SHILO and SHILOV helper_shilo has not been shifting an accumulator value correctly for negative values in 'shift' field. Minor optimization for shift=0 case. This change also adds tests that will trigger issue and check for regressions. Signed-off-by: Petar Jovanovic Reviewed-by: Richard Henderson Reviewed-by: Eric Johnson Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 17 +++++++++-------- tests/tcg/mips/mips32-dsp/shilo.c | 18 ++++++++++++++++++ tests/tcg/mips/mips32-dsp/shilov.c | 20 ++++++++++++++++++++ 3 files changed, 47 insertions(+), 8 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index fda5f0460b..14daf91950 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env) rs5_0 = rs & 0x3F; rs5_0 = (int8_t)(rs5_0 << 2) >> 2; - rs5_0 = MIPSDSP_ABS(rs5_0); + + if (unlikely(rs5_0 == 0)) { + return; + } + acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) | ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); - if (rs5_0 == 0) { - temp = acc; + + if (rs5_0 > 0) { + temp = acc >> rs5_0; } else { - if (rs5_0 > 0) { - temp = acc >> rs5_0; - } else { - temp = acc << rs5_0; - } + temp = acc << -rs5_0; } env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32); diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-dsp/shilo.c index b686616d80..ce8ebc69c2 100644 --- a/tests/tcg/mips/mips32-dsp/shilo.c +++ b/tests/tcg/mips/mips32-dsp/shilo.c @@ -23,5 +23,23 @@ int main() assert(ach == resulth); assert(acl == resultl); + + ach = 0x1; + acl = 0x80000000; + + resulth = 0x3; + resultl = 0x0; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilo $ac1, -1\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + ); + assert(ach == resulth); + assert(acl == resultl); + return 0; } diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-dsp/shilov.c index f186032a14..e1d6cea4b6 100644 --- a/tests/tcg/mips/mips32-dsp/shilov.c +++ b/tests/tcg/mips/mips32-dsp/shilov.c @@ -25,5 +25,25 @@ int main() assert(ach == resulth); assert(acl == resultl); + + rs = 0xffffffff; + ach = 0x1; + acl = 0x80000000; + + resulth = 0x3; + resultl = 0x0; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilov $ac1, %2\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs) + ); + assert(ach == resulth); + assert(acl == resultl); + return 0; }