mirror of https://github.com/xemu-project/xemu.git
target/loongarch: Implement xvsrlrn xvsrarn
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-40-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
40c7674e9e
commit
c50ce38a47
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@ -2120,6 +2120,22 @@ INSN_LASX(xvsrani_h_w, vv_i)
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INSN_LASX(xvsrani_w_d, vv_i)
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INSN_LASX(xvsrani_d_q, vv_i)
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INSN_LASX(xvsrlrn_b_h, vvv)
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INSN_LASX(xvsrlrn_h_w, vvv)
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INSN_LASX(xvsrlrn_w_d, vvv)
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INSN_LASX(xvsrarn_b_h, vvv)
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INSN_LASX(xvsrarn_h_w, vvv)
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INSN_LASX(xvsrarn_w_d, vvv)
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INSN_LASX(xvsrlrni_b_h, vv_i)
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INSN_LASX(xvsrlrni_h_w, vv_i)
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INSN_LASX(xvsrlrni_w_d, vv_i)
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INSN_LASX(xvsrlrni_d_q, vv_i)
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INSN_LASX(xvsrarni_b_h, vv_i)
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INSN_LASX(xvsrarni_h_w, vv_i)
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INSN_LASX(xvsrarni_w_d, vv_i)
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INSN_LASX(xvsrarni_d_q, vv_i)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -3801,6 +3801,12 @@ TRANS(vsrlrn_w_d, LSX, gen_vvv, gen_helper_vsrlrn_w_d)
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TRANS(vsrarn_b_h, LSX, gen_vvv, gen_helper_vsrarn_b_h)
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TRANS(vsrarn_h_w, LSX, gen_vvv, gen_helper_vsrarn_h_w)
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TRANS(vsrarn_w_d, LSX, gen_vvv, gen_helper_vsrarn_w_d)
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TRANS(xvsrlrn_b_h, LASX, gen_xxx, gen_helper_vsrlrn_b_h)
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TRANS(xvsrlrn_h_w, LASX, gen_xxx, gen_helper_vsrlrn_h_w)
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TRANS(xvsrlrn_w_d, LASX, gen_xxx, gen_helper_vsrlrn_w_d)
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TRANS(xvsrarn_b_h, LASX, gen_xxx, gen_helper_vsrarn_b_h)
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TRANS(xvsrarn_h_w, LASX, gen_xxx, gen_helper_vsrarn_h_w)
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TRANS(xvsrarn_w_d, LASX, gen_xxx, gen_helper_vsrarn_w_d)
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TRANS(vsrlrni_b_h, LSX, gen_vv_i, gen_helper_vsrlrni_b_h)
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TRANS(vsrlrni_h_w, LSX, gen_vv_i, gen_helper_vsrlrni_h_w)
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@ -3810,6 +3816,14 @@ TRANS(vsrarni_b_h, LSX, gen_vv_i, gen_helper_vsrarni_b_h)
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TRANS(vsrarni_h_w, LSX, gen_vv_i, gen_helper_vsrarni_h_w)
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TRANS(vsrarni_w_d, LSX, gen_vv_i, gen_helper_vsrarni_w_d)
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TRANS(vsrarni_d_q, LSX, gen_vv_i, gen_helper_vsrarni_d_q)
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TRANS(xvsrlrni_b_h, LASX, gen_xx_i, gen_helper_vsrlrni_b_h)
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TRANS(xvsrlrni_h_w, LASX, gen_xx_i, gen_helper_vsrlrni_h_w)
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TRANS(xvsrlrni_w_d, LASX, gen_xx_i, gen_helper_vsrlrni_w_d)
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TRANS(xvsrlrni_d_q, LASX, gen_xx_i, gen_helper_vsrlrni_d_q)
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TRANS(xvsrarni_b_h, LASX, gen_xx_i, gen_helper_vsrarni_b_h)
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TRANS(xvsrarni_h_w, LASX, gen_xx_i, gen_helper_vsrarni_h_w)
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TRANS(xvsrarni_w_d, LASX, gen_xx_i, gen_helper_vsrarni_w_d)
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TRANS(xvsrarni_d_q, LASX, gen_xx_i, gen_helper_vsrarni_d_q)
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TRANS(vssrln_b_h, LSX, gen_vvv, gen_helper_vssrln_b_h)
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TRANS(vssrln_h_w, LSX, gen_vvv, gen_helper_vssrln_h_w)
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@ -1694,6 +1694,22 @@ xvsrani_h_w 0111 01110101 10001 ..... ..... ..... @vv_ui5
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xvsrani_w_d 0111 01110101 1001 ...... ..... ..... @vv_ui6
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xvsrani_d_q 0111 01110101 101 ....... ..... ..... @vv_ui7
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xvsrlrn_b_h 0111 01001111 10001 ..... ..... ..... @vvv
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xvsrlrn_h_w 0111 01001111 10010 ..... ..... ..... @vvv
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xvsrlrn_w_d 0111 01001111 10011 ..... ..... ..... @vvv
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xvsrarn_b_h 0111 01001111 10101 ..... ..... ..... @vvv
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xvsrarn_h_w 0111 01001111 10110 ..... ..... ..... @vvv
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xvsrarn_w_d 0111 01001111 10111 ..... ..... ..... @vvv
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xvsrlrni_b_h 0111 01110100 01000 1 .... ..... ..... @vv_ui4
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xvsrlrni_h_w 0111 01110100 01001 ..... ..... ..... @vv_ui5
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xvsrlrni_w_d 0111 01110100 0101 ...... ..... ..... @vv_ui6
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xvsrlrni_d_q 0111 01110100 011 ....... ..... ..... @vv_ui7
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xvsrarni_b_h 0111 01110101 11000 1 .... ..... ..... @vv_ui4
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xvsrarni_h_w 0111 01110101 11001 ..... ..... ..... @vv_ui5
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xvsrarni_w_d 0111 01110101 1101 ...... ..... ..... @vv_ui6
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xvsrarni_d_q 0111 01110101 111 ....... ..... ..... @vv_ui7
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -1231,76 +1231,95 @@ VSRANI(vsrani_b_h, 16, B, H)
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VSRANI(vsrani_h_w, 32, H, W)
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VSRANI(vsrani_w_d, 64, W, D)
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#define VSRLRN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_vsrlr_ ## E2(Vj->E2(i), ((T)Vk->E2(i))%BIT); \
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} \
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Vd->D(1) = 0; \
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#define VSRLRN(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_vsrlr_ ##E2(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSRLRN(vsrlrn_b_h, 16, uint16_t, B, H)
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VSRLRN(vsrlrn_h_w, 32, uint32_t, H, W)
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VSRLRN(vsrlrn_w_d, 64, uint64_t, W, D)
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VSRLRN(vsrlrn_b_h, 16, B, H, UH)
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VSRLRN(vsrlrn_h_w, 32, H, W, UW)
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VSRLRN(vsrlrn_w_d, 64, W, D, UD)
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#define VSRARN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_vsrar_ ## E2(Vj->E2(i), ((T)Vk->E2(i))%BIT); \
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} \
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Vd->D(1) = 0; \
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#define VSRARN(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_vsrar_ ## E2(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSRARN(vsrarn_b_h, 16, uint8_t, B, H)
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VSRARN(vsrarn_h_w, 32, uint16_t, H, W)
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VSRARN(vsrarn_w_d, 64, uint32_t, W, D)
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VSRARN(vsrarn_b_h, 16, B, H, UH)
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VSRARN(vsrarn_h_w, 32, H, W, UW)
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VSRARN(vsrarn_w_d, 64, W, D, UD)
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#define VSRLRNI(NAME, BIT, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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{ \
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int i, max; \
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VReg temp; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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\
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temp.D(0) = 0; \
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temp.D(1) = 0; \
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max = LSX_LEN/BIT; \
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for (i = 0; i < max; i++) { \
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temp.E1(i) = do_vsrlr_ ## E2(Vj->E2(i), imm); \
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temp.E1(i + max) = do_vsrlr_ ## E2(Vd->E2(i), imm); \
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} \
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*Vd = temp; \
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#define VSRLRNI(NAME, BIT, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg temp = {}; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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temp.E1(j + ofs * 2 * i) = do_vsrlr_ ## E2(Vj->E2(j + ofs * i), imm); \
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temp.E1(j + ofs * (2 * i + 1)) = do_vsrlr_ ## E2(Vd->E2(j + ofs * i), \
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imm); \
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} \
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} \
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*Vd = temp; \
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}
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void HELPER(vsrlrni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
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{
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VReg temp;
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int i;
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VReg temp = {};
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VReg *Vd = (VReg *)vd;
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VReg *Vj = (VReg *)vj;
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Int128 r1, r2;
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Int128 r[4];
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int oprsz = simd_oprsz(desc);
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if (imm == 0) {
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temp.D(0) = int128_getlo(Vj->Q(0));
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temp.D(1) = int128_getlo(Vd->Q(0));
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} else {
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r1 = int128_and(int128_urshift(Vj->Q(0), (imm -1)), int128_one());
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r2 = int128_and(int128_urshift(Vd->Q(0), (imm -1)), int128_one());
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temp.D(0) = int128_getlo(int128_add(int128_urshift(Vj->Q(0), imm), r1));
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temp.D(1) = int128_getlo(int128_add(int128_urshift(Vd->Q(0), imm), r2));
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for (i = 0; i < oprsz / 16; i++) {
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if (imm == 0) {
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temp.D(2 * i) = int128_getlo(Vj->Q(i));
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temp.D(2 * i + 1) = int128_getlo(Vd->Q(i));
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} else {
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r[2 * i] = int128_and(int128_urshift(Vj->Q(i), (imm - 1)),
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int128_one());
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r[2 * i + 1] = int128_and(int128_urshift(Vd->Q(i), (imm - 1)),
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int128_one());
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temp.D(2 * i) = int128_getlo(int128_add(int128_urshift(Vj->Q(i),
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imm), r[2 * i]));
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temp.D(2 * i + 1) = int128_getlo(int128_add(int128_urshift(Vd->Q(i),
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imm), r[ 2 * i + 1]));
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}
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}
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*Vd = temp;
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}
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@ -1309,40 +1328,49 @@ VSRLRNI(vsrlrni_b_h, 16, B, H)
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VSRLRNI(vsrlrni_h_w, 32, H, W)
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VSRLRNI(vsrlrni_w_d, 64, W, D)
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#define VSRARNI(NAME, BIT, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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{ \
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int i, max; \
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VReg temp; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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\
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temp.D(0) = 0; \
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temp.D(1) = 0; \
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max = LSX_LEN/BIT; \
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for (i = 0; i < max; i++) { \
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temp.E1(i) = do_vsrar_ ## E2(Vj->E2(i), imm); \
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temp.E1(i + max) = do_vsrar_ ## E2(Vd->E2(i), imm); \
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} \
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*Vd = temp; \
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#define VSRARNI(NAME, BIT, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg temp = {}; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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temp.E1(j + ofs * 2 * i) = do_vsrar_ ## E2(Vj->E2(j + ofs * i), imm); \
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temp.E1(j + ofs * (2 * i + 1)) = do_vsrar_ ## E2(Vd->E2(j + ofs * i), \
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imm); \
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} \
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} \
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*Vd = temp; \
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}
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void HELPER(vsrarni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
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{
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VReg temp;
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int i;
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VReg temp = {};
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VReg *Vd = (VReg *)vd;
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VReg *Vj = (VReg *)vj;
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Int128 r1, r2;
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Int128 r[4];
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int oprsz = simd_oprsz(desc);
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if (imm == 0) {
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temp.D(0) = int128_getlo(Vj->Q(0));
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temp.D(1) = int128_getlo(Vd->Q(0));
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} else {
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r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
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r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
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temp.D(0) = int128_getlo(int128_add(int128_rshift(Vj->Q(0), imm), r1));
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temp.D(1) = int128_getlo(int128_add(int128_rshift(Vd->Q(0), imm), r2));
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for (i = 0; i < oprsz / 16; i++) {
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if (imm == 0) {
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temp.D(2 * i) = int128_getlo(Vj->Q(i));
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temp.D(2 * i + 1) = int128_getlo(Vd->Q(i));
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} else {
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r[2 * i] = int128_and(int128_rshift(Vj->Q(i), (imm - 1)),
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int128_one());
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r[2 * i + 1] = int128_and(int128_rshift(Vd->Q(i), (imm - 1)),
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int128_one());
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temp.D(2 * i) = int128_getlo(int128_add(int128_rshift(Vj->Q(i),
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imm), r[2 * i]));
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temp.D(2 * i + 1) = int128_getlo(int128_add(int128_rshift(Vd->Q(i),
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imm), r[2 * i + 1]));
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}
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}
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*Vd = temp;
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}
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