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target/riscv: add support for Zcd extension 

Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:13:57 +08:00 committed by Alistair Francis
parent 30b0357902
commit c4935b5842
2 changed files with 22 additions and 4 deletions
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8
target/riscv/insn16.decode
View File

@ -97,12 +97,12 @@
} }
{ {
lq 001 ... ... .. ... 00 @cl_q lq 001 ... ... .. ... 00 @cl_q
fld 001 ... ... .. ... 00 @cl_d c_fld 001 ... ... .. ... 00 @cl_d
} }
lw 010 ... ... .. ... 00 @cl_w lw 010 ... ... .. ... 00 @cl_w
{ {
sq 101 ... ... .. ... 00 @cs_q sq 101 ... ... .. ... 00 @cs_q
fsd 101 ... ... .. ... 00 @cs_d c_fsd 101 ... ... .. ... 00 @cs_d
} }
sw 110 ... ... .. ... 00 @cs_w sw 110 ... ... .. ... 00 @cs_w
@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2
slli 000 . ..... ..... 10 @c_shift2 slli 000 . ..... ..... 10 @c_shift2
{ {
lq 001 ... ... .. ... 10 @c_lqsp lq 001 ... ... .. ... 10 @c_lqsp
fld 001 . ..... ..... 10 @c_ldsp c_fld 001 . ..... ..... 10 @c_ldsp
} }
{ {
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2
} }
{ {
sq 101 ... ... .. ... 10 @c_sqsp sq 101 ... ... .. ... 10 @c_sqsp
fsd 101 ...... ..... 10 @c_sdsp c_fsd 101 ...... ..... 10 @c_sdsp
} }
sw 110 . ..... ..... 10 @c_swsp sw 110 . ..... ..... 10 @c_swsp

18
target/riscv/insn_trans/trans_rvd.c.inc
View File

@ -31,6 +31,12 @@
} \ } \
} while (0) } while (0)
#define REQUIRE_ZCD(ctx) do { \
if (!ctx->cfg_ptr->ext_zcd) { \
return false; \
} \
} while (0)
static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fld(DisasContext *ctx, arg_fld *a)
{ {
TCGv addr; TCGv addr;
@ -59,6 +65,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
return true; return true;
} }
static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
{
REQUIRE_ZCD(ctx);
return trans_fld(ctx, a);
}
static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
{
REQUIRE_ZCD(ctx);
return trans_fsd(ctx, a);
}
static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
{ {
REQUIRE_FPU; REQUIRE_FPU;