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target/arm: Change gen_*set_pc_im to gen_*update_pc 

In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-20 13:06:35 +10:00 committed by Peter Maydell
parent 168122419e
commit c44c8b8b99
5 changed files with 56 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/arm/translate-a32.h
View File

@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
void gen_set_condexec(DisasContext *s); void gen_set_condexec(DisasContext *s);
void gen_set_pc_im(DisasContext *s, target_ulong val); void gen_update_pc(DisasContext *s, target_long diff);
void gen_lookup_tb(DisasContext *s); void gen_lookup_tb(DisasContext *s);
long vfp_reg_offset(bool dp, unsigned reg); long vfp_reg_offset(bool dp, unsigned reg);
long neon_full_reg_offset(unsigned reg); long neon_full_reg_offset(unsigned reg);

32
target/arm/translate-a64.c
View File

@ -140,9 +140,9 @@ static void reset_btype(DisasContext *s)
} }
} }
void gen_a64_set_pc_im(uint64_t val) void gen_a64_update_pc(DisasContext *s, target_long diff)
{ {
tcg_gen_movi_i64(cpu_pc, val); tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
} }
/* /*
@ -334,14 +334,14 @@ static void gen_exception_internal(int excp)
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
{ {
gen_a64_set_pc_im(pc); gen_a64_update_pc(s, pc - s->pc_curr);
gen_exception_internal(excp); gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
{ {
gen_a64_set_pc_im(s->pc_curr); gen_a64_update_pc(s, 0);
gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -376,11 +376,11 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
if (use_goto_tb(s, dest)) { if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n); tcg_gen_goto_tb(n);
gen_a64_set_pc_im(dest); gen_a64_update_pc(s, diff);
tcg_gen_exit_tb(s->base.tb, n); tcg_gen_exit_tb(s->base.tb, n);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} else { } else {
gen_a64_set_pc_im(dest); gen_a64_update_pc(s, diff);
if (s->ss_active) { if (s->ss_active) {
gen_step_complete_exception(s); gen_step_complete_exception(s);
} else { } else {
@ -1952,7 +1952,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
uint32_t syndrome; uint32_t syndrome;
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
gen_a64_set_pc_im(s->pc_curr); gen_a64_update_pc(s, 0);
gen_helper_access_check_cp_reg(cpu_env, gen_helper_access_check_cp_reg(cpu_env,
tcg_constant_ptr(ri), tcg_constant_ptr(ri),
tcg_constant_i32(syndrome), tcg_constant_i32(syndrome),
@ -1962,7 +1962,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
* The readfn or writefn might raise an exception; * The readfn or writefn might raise an exception;
* synchronize the CPU state in case it does. * synchronize the CPU state in case it does.
*/ */
gen_a64_set_pc_im(s->pc_curr); gen_a64_update_pc(s, 0);
} }
/* Handle special cases first */ /* Handle special cases first */
@ -2172,7 +2172,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
/* The pre HVC helper handles cases when HVC gets trapped /* The pre HVC helper handles cases when HVC gets trapped
* as an undefined insn by runtime configuration. * as an undefined insn by runtime configuration.
*/ */
gen_a64_set_pc_im(s->pc_curr); gen_a64_update_pc(s, 0);
gen_helper_pre_hvc(cpu_env); gen_helper_pre_hvc(cpu_env);
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
@ -2183,7 +2183,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
unallocated_encoding(s); unallocated_encoding(s);
break; break;
} }
gen_a64_set_pc_im(s->pc_curr); gen_a64_update_pc(s, 0);
gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
@ -14935,7 +14935,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
*/ */
switch (dc->base.is_jmp) { switch (dc->base.is_jmp) {
default: default:
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_update_pc(dc, 4);
/* fall through */ /* fall through */
case DISAS_EXIT: case DISAS_EXIT:
case DISAS_JUMP: case DISAS_JUMP:
@ -14952,13 +14952,13 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
break; break;
default: default:
case DISAS_UPDATE_EXIT: case DISAS_UPDATE_EXIT:
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_update_pc(dc, 4);
/* fall through */ /* fall through */
case DISAS_EXIT: case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
break; break;
case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_NOCHAIN:
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_update_pc(dc, 4);
/* fall through */ /* fall through */
case DISAS_JUMP: case DISAS_JUMP:
tcg_gen_lookup_and_goto_ptr(); tcg_gen_lookup_and_goto_ptr();
@ -14967,11 +14967,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
case DISAS_SWI: case DISAS_SWI:
break; break;
case DISAS_WFE: case DISAS_WFE:
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_update_pc(dc, 4);
gen_helper_wfe(cpu_env); gen_helper_wfe(cpu_env);
break; break;
case DISAS_YIELD: case DISAS_YIELD:
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_update_pc(dc, 4);
gen_helper_yield(cpu_env); gen_helper_yield(cpu_env);
break; break;
case DISAS_WFI: case DISAS_WFI:
@ -14979,7 +14979,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
* This is a special case because we don't want to just halt * This is a special case because we don't want to just halt
* the CPU if trying to debug across a WFI. * the CPU if trying to debug across a WFI.
*/ */
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_update_pc(dc, 4);
gen_helper_wfi(cpu_env, tcg_constant_i32(4)); gen_helper_wfi(cpu_env, tcg_constant_i32(4));
/* /*
* The helper doesn't necessarily throw an exception, but we * The helper doesn't necessarily throw an exception, but we

2
target/arm/translate-vfp.c
View File

@ -856,7 +856,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
case ARM_VFP_FPSID: case ARM_VFP_FPSID:
if (s->current_el == 1) { if (s->current_el == 1) {
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
gen_helper_check_hcr_el2_trap(cpu_env, gen_helper_check_hcr_el2_trap(cpu_env,
tcg_constant_i32(a->rt), tcg_constant_i32(a->rt),
tcg_constant_i32(a->reg)); tcg_constant_i32(a->reg));

68
target/arm/translate.c
View File

@ -768,9 +768,9 @@ void gen_set_condexec(DisasContext *s)
} }
} }
void gen_set_pc_im(DisasContext *s, target_ulong val) void gen_update_pc(DisasContext *s, target_long diff)
{ {
tcg_gen_movi_i32(cpu_R[15], val); tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff);
} }
/* Set PC and Thumb state from var. var is marked as dead. */ /* Set PC and Thumb state from var. var is marked as dead. */
@ -862,7 +862,7 @@ static inline void gen_bxns(DisasContext *s, int rm)
/* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
* we need to sync state before calling it, but: * we need to sync state before calling it, but:
* - we don't need to do gen_set_pc_im() because the bxns helper will * - we don't need to do gen_update_pc() because the bxns helper will
* always set the PC itself * always set the PC itself
* - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
* unless it's outside an IT block or the last insn in an IT block, * unless it's outside an IT block or the last insn in an IT block,
@ -883,7 +883,7 @@ static inline void gen_blxns(DisasContext *s, int rm)
* We do however need to set the PC, because the blxns helper reads it. * We do however need to set the PC, because the blxns helper reads it.
* The blxns helper may throw an exception. * The blxns helper may throw an exception.
*/ */
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
gen_helper_v7m_blxns(cpu_env, var); gen_helper_v7m_blxns(cpu_env, var);
tcg_temp_free_i32(var); tcg_temp_free_i32(var);
s->base.is_jmp = DISAS_EXIT; s->base.is_jmp = DISAS_EXIT;
@ -1051,7 +1051,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
* as an undefined insn by runtime configuration (ie before * as an undefined insn by runtime configuration (ie before
* the insn really executes). * the insn really executes).
*/ */
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
gen_helper_pre_hvc(cpu_env); gen_helper_pre_hvc(cpu_env);
/* Otherwise we will treat this as a real exception which /* Otherwise we will treat this as a real exception which
* happens after execution of the insn. (The distinction matters * happens after execution of the insn. (The distinction matters
@ -1059,7 +1059,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
* for single stepping.) * for single stepping.)
*/ */
s->svc_imm = imm16; s->svc_imm = imm16;
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_HVC; s->base.is_jmp = DISAS_HVC;
} }
@ -1068,16 +1068,16 @@ static inline void gen_smc(DisasContext *s)
/* As with HVC, we may take an exception either before or after /* As with HVC, we may take an exception either before or after
* the insn executes. * the insn executes.
*/ */
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_SMC; s->base.is_jmp = DISAS_SMC;
} }
static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
{ {
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, pc); gen_update_pc(s, pc - s->pc_curr);
gen_exception_internal(excp); gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -1103,10 +1103,10 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
uint32_t syn, TCGv_i32 tcg_el) uint32_t syn, TCGv_i32 tcg_el)
{ {
if (s->aarch64) { if (s->aarch64) {
gen_a64_set_pc_im(pc); gen_a64_update_pc(s, pc - s->pc_curr);
} else { } else {
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, pc); gen_update_pc(s, pc - s->pc_curr);
} }
gen_exception_el_v(excp, syn, tcg_el); gen_exception_el_v(excp, syn, tcg_el);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
@ -1121,10 +1121,10 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
{ {
if (s->aarch64) { if (s->aarch64) {
gen_a64_set_pc_im(pc); gen_a64_update_pc(s, pc - s->pc_curr);
} else { } else {
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, pc); gen_update_pc(s, pc - s->pc_curr);
} }
gen_exception(excp, syn); gen_exception(excp, syn);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
@ -1133,7 +1133,7 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
{ {
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -2596,10 +2596,10 @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
if (translator_use_goto_tb(&s->base, dest)) { if (translator_use_goto_tb(&s->base, dest)) {
tcg_gen_goto_tb(n); tcg_gen_goto_tb(n);
gen_set_pc_im(s, dest); gen_update_pc(s, diff);
tcg_gen_exit_tb(s->base.tb, n); tcg_gen_exit_tb(s->base.tb, n);
} else { } else {
gen_set_pc_im(s, dest); gen_update_pc(s, diff);
gen_goto_ptr(); gen_goto_ptr();
} }
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
@ -2608,9 +2608,11 @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
/* Jump, specifying which TB number to use if we gen_goto_tb() */ /* Jump, specifying which TB number to use if we gen_goto_tb() */
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
{ {
int diff = dest - s->pc_curr;
if (unlikely(s->ss_active)) { if (unlikely(s->ss_active)) {
/* An indirect jump so that we still trigger the debug exception. */ /* An indirect jump so that we still trigger the debug exception. */
gen_set_pc_im(s, dest); gen_update_pc(s, diff);
s->base.is_jmp = DISAS_JUMP; s->base.is_jmp = DISAS_JUMP;
return; return;
} }
@ -2627,7 +2629,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
* gen_jmp(); * gen_jmp();
* on the second call to gen_jmp(). * on the second call to gen_jmp().
*/ */
gen_goto_tb(s, tbno, dest - s->pc_curr); gen_goto_tb(s, tbno, diff);
break; break;
case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_NOCHAIN:
case DISAS_UPDATE_EXIT: case DISAS_UPDATE_EXIT:
@ -2636,7 +2638,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
* Avoid using goto_tb so we really do exit back to the main loop * Avoid using goto_tb so we really do exit back to the main loop
* and don't chain to another TB. * and don't chain to another TB.
*/ */
gen_set_pc_im(s, dest); gen_update_pc(s, diff);
gen_goto_ptr(); gen_goto_ptr();
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
break; break;
@ -2904,7 +2906,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
/* Sync state because msr_banked() can raise exceptions */ /* Sync state because msr_banked() can raise exceptions */
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
tcg_reg = load_reg(s, rn); tcg_reg = load_reg(s, rn);
gen_helper_msr_banked(cpu_env, tcg_reg, gen_helper_msr_banked(cpu_env, tcg_reg,
tcg_constant_i32(tgtmode), tcg_constant_i32(tgtmode),
@ -2924,7 +2926,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
/* Sync state because mrs_banked() can raise exceptions */ /* Sync state because mrs_banked() can raise exceptions */
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
tcg_reg = tcg_temp_new_i32(); tcg_reg = tcg_temp_new_i32();
gen_helper_mrs_banked(tcg_reg, cpu_env, gen_helper_mrs_banked(tcg_reg, cpu_env,
tcg_constant_i32(tgtmode), tcg_constant_i32(tgtmode),
@ -4745,7 +4747,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
} }
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
gen_helper_access_check_cp_reg(cpu_env, gen_helper_access_check_cp_reg(cpu_env,
tcg_constant_ptr(ri), tcg_constant_ptr(ri),
tcg_constant_i32(syndrome), tcg_constant_i32(syndrome),
@ -4756,7 +4758,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
* synchronize the CPU state in case it does. * synchronize the CPU state in case it does.
*/ */
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
} }
/* Handle special cases first */ /* Handle special cases first */
@ -4770,7 +4772,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_WFI; s->base.is_jmp = DISAS_WFI;
return; return;
default: default:
@ -5157,7 +5159,7 @@ static void gen_srs(DisasContext *s,
addr = tcg_temp_new_i32(); addr = tcg_temp_new_i32();
/* get_r13_banked() will raise an exception if called from System mode */ /* get_r13_banked() will raise an exception if called from System mode */
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_update_pc(s, 0);
gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
switch (amode) { switch (amode) {
case 0: /* DA */ case 0: /* DA */
@ -6226,7 +6228,7 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
* scheduling of other vCPUs. * scheduling of other vCPUs.
*/ */
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_YIELD; s->base.is_jmp = DISAS_YIELD;
} }
return true; return true;
@ -6242,7 +6244,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
* implemented so we can't sleep like WFI does. * implemented so we can't sleep like WFI does.
*/ */
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_WFE; s->base.is_jmp = DISAS_WFE;
} }
return true; return true;
@ -6251,7 +6253,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
static bool trans_WFI(DisasContext *s, arg_WFI *a) static bool trans_WFI(DisasContext *s, arg_WFI *a)
{ {
/* For WFI, halt the vCPU until an IRQ. */ /* For WFI, halt the vCPU until an IRQ. */
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_WFI; s->base.is_jmp = DISAS_WFI;
return true; return true;
} }
@ -8761,7 +8763,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
(a->imm == semihost_imm)) { (a->imm == semihost_imm)) {
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
} else { } else {
gen_set_pc_im(s, s->base.pc_next); gen_update_pc(s, curr_insn_len(s));
s->svc_imm = a->imm; s->svc_imm = a->imm;
s->base.is_jmp = DISAS_SWI; s->base.is_jmp = DISAS_SWI;
} }
@ -9774,7 +9776,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
case DISAS_TOO_MANY: case DISAS_TOO_MANY:
case DISAS_UPDATE_EXIT: case DISAS_UPDATE_EXIT:
case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_NOCHAIN:
gen_set_pc_im(dc, dc->base.pc_next); gen_update_pc(dc, curr_insn_len(dc));
/* fall through */ /* fall through */
default: default:
/* FIXME: Single stepping a WFI insn will not halt the CPU. */ /* FIXME: Single stepping a WFI insn will not halt the CPU. */
@ -9798,13 +9800,13 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_goto_tb(dc, 1, curr_insn_len(dc)); gen_goto_tb(dc, 1, curr_insn_len(dc));
break; break;
case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_NOCHAIN:
gen_set_pc_im(dc, dc->base.pc_next); gen_update_pc(dc, curr_insn_len(dc));
/* fall through */ /* fall through */
case DISAS_JUMP: case DISAS_JUMP:
gen_goto_ptr(); gen_goto_ptr();
break; break;
case DISAS_UPDATE_EXIT: case DISAS_UPDATE_EXIT:
gen_set_pc_im(dc, dc->base.pc_next); gen_update_pc(dc, curr_insn_len(dc));
/* fall through */ /* fall through */
default: default:
/* indicate that the hash table must be used to find the next TB */ /* indicate that the hash table must be used to find the next TB */
@ -9844,7 +9846,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_set_label(dc->condlabel); gen_set_label(dc->condlabel);
gen_set_condexec(dc); gen_set_condexec(dc);
if (unlikely(dc->ss_active)) { if (unlikely(dc->ss_active)) {
gen_set_pc_im(dc, dc->base.pc_next); gen_update_pc(dc, curr_insn_len(dc));
gen_singlestep_exception(dc); gen_singlestep_exception(dc);
} else { } else {
gen_goto_tb(dc, 1, curr_insn_len(dc)); gen_goto_tb(dc, 1, curr_insn_len(dc));

6
target/arm/translate.h
View File

@ -254,7 +254,7 @@ static inline int curr_insn_len(DisasContext *s)
* For instructions which want an immediate exit to the main loop, as opposed * For instructions which want an immediate exit to the main loop, as opposed
* to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
* doesn't write the PC on exiting the translation loop so you need to ensure * doesn't write the PC on exiting the translation loop so you need to ensure
* something (gen_a64_set_pc_im or runtime helper) has done so before we reach * something (gen_a64_update_pc or runtime helper) has done so before we reach
* return from cpu_tb_exec. * return from cpu_tb_exec.
*/ */
#define DISAS_EXIT DISAS_TARGET_9 #define DISAS_EXIT DISAS_TARGET_9
@ -263,14 +263,14 @@ static inline int curr_insn_len(DisasContext *s)
#ifdef TARGET_AARCH64 #ifdef TARGET_AARCH64
void a64_translate_init(void); void a64_translate_init(void);
void gen_a64_set_pc_im(uint64_t val); void gen_a64_update_pc(DisasContext *s, target_long diff);
extern const TranslatorOps aarch64_translator_ops; extern const TranslatorOps aarch64_translator_ops;
#else #else
static inline void a64_translate_init(void) static inline void a64_translate_init(void)
{ {
} }
static inline void gen_a64_set_pc_im(uint64_t val) static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
{ {
} }
#endif #endif