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hw/intc: ibex_plic: Update the pending irqs 

After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
5576582280 "riscv: plic: Add a couple of mising
sifive_plic_update calls"

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis 2020-07-24 22:34:40 -07:00
parent af3fc195e3
commit c43388bbfd
1 changed files with 4 additions and 0 deletions
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4
hw/intc/ibex_plic.c
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@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
s->pending[pending_num] &= ~(1 << (s->claim % 32)); s->pending[pending_num] &= ~(1 << (s->claim % 32));
ret = s->claim; ret = s->claim;
/* Update the interrupt status after the claim */
ibex_plic_update(s);
} }
return ret; return ret;
@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
} else if (addr_between(addr, s->priority_base, s->priority_num)) { } else if (addr_between(addr, s->priority_base, s->priority_num)) {
uint32_t irq = ((addr - s->priority_base) >> 2) + 1; uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
s->priority[irq] = value & 7; s->priority[irq] = value & 7;
ibex_plic_update(s);
} else if (addr_between(addr, s->enable_base, s->enable_num)) { } else if (addr_between(addr, s->enable_base, s->enable_num)) {
uint32_t enable_reg = (addr - s->enable_base) / 4; uint32_t enable_reg = (addr - s->enable_base) / 4;