mirror of https://github.com/xemu-project/xemu.git
Merge remote-tracking branch 'bonzini/iommu-for-anthony' into staging
# By Paolo Bonzini (50) and others # Via Paolo Bonzini * bonzini/iommu-for-anthony: (66 commits) exec: change some APIs to take AddressSpaceDispatch exec: remove cur_map exec: put memory map in AddressSpaceDispatch exec: separate current radix tree from the one being built exec: move listener from AddressSpaceDispatch to AddressSpace memory: move MemoryListener declaration earlier exec: separate current memory map from the one being built exec: change well-known physical sections to macros qom: Use atomics for object refcounting memory: add reference counting to FlatView memory: use a new FlatView pointer on every topology update memory: access FlatView from a local variable add a header file for atomic operations hw/[u-x]*: pass owner to memory_region_init* functions hw/t*: pass owner to memory_region_init* functions hw/s*: pass owner to memory_region_init* functions hw/p*: pass owner to memory_region_init* functions hw/n*: pass owner to memory_region_init* functions hw/m*: pass owner to memory_region_init* functions hw/i*: pass owner to memory_region_init* functions ... Message-id: 1372950842-32422-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
commit
c3ab4c9cf2
11
cputlb.c
11
cputlb.c
|
|
@ -158,6 +158,17 @@ void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
|
|||
}
|
||||
}
|
||||
|
||||
static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
|
||||
{
|
||||
ram_addr_t ram_addr;
|
||||
|
||||
if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
|
||||
fprintf(stderr, "Bad ram pointer %p\n", ptr);
|
||||
abort();
|
||||
}
|
||||
return ram_addr;
|
||||
}
|
||||
|
||||
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
|
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{
|
||||
ram_addr_t ram_addr;
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||||
|
|
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|||
|
|
@ -34,13 +34,16 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
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return error;
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||||
}
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|
||||
void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, AddressSpace *as)
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void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
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||||
AddressSpace *as)
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||||
{
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qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
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qsg->nsg = 0;
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qsg->nalloc = alloc_hint;
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qsg->size = 0;
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qsg->as = as;
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qsg->dev = dev;
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object_ref(OBJECT(dev));
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}
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void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
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|
|
@ -57,6 +60,7 @@ void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
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void qemu_sglist_destroy(QEMUSGList *qsg)
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{
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||||
object_unref(OBJECT(qsg->dev));
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g_free(qsg->sg);
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memset(qsg, 0, sizeof(*qsg));
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}
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|
|
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|
@ -0,0 +1,352 @@
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CPUs perform independent memory operations effectively in random order.
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||||
but this can be a problem for CPU-CPU interaction (including interactions
|
||||
between QEMU and the guest). Multi-threaded programs use various tools
|
||||
to instruct the compiler and the CPU to restrict the order to something
|
||||
that is consistent with the expectations of the programmer.
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||||
|
||||
The most basic tool is locking. Mutexes, condition variables and
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||||
semaphores are used in QEMU, and should be the default approach to
|
||||
synchronization. Anything else is considerably harder, but it's
|
||||
also justified more often than one would like. The two tools that
|
||||
are provided by qemu/atomic.h are memory barriers and atomic operations.
|
||||
|
||||
Macros defined by qemu/atomic.h fall in three camps:
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||||
|
||||
- compiler barriers: barrier();
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||||
|
||||
- weak atomic access and manual memory barriers: atomic_read(),
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||||
atomic_set(), smp_rmb(), smp_wmb(), smp_mb(), smp_read_barrier_depends();
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||||
|
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- sequentially consistent atomic access: everything else.
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|
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|
||||
COMPILER MEMORY BARRIER
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||||
=======================
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||||
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barrier() prevents the compiler from moving the memory accesses either
|
||||
side of it to the other side. The compiler barrier has no direct effect
|
||||
on the CPU, which may then reorder things however it wishes.
|
||||
|
||||
barrier() is mostly used within qemu/atomic.h itself. On some
|
||||
architectures, CPU guarantees are strong enough that blocking compiler
|
||||
optimizations already ensures the correct order of execution. In this
|
||||
case, qemu/atomic.h will reduce stronger memory barriers to simple
|
||||
compiler barriers.
|
||||
|
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Still, barrier() can be useful when writing code that can be interrupted
|
||||
by signal handlers.
|
||||
|
||||
|
||||
SEQUENTIALLY CONSISTENT ATOMIC ACCESS
|
||||
=====================================
|
||||
|
||||
Most of the operations in the qemu/atomic.h header ensure *sequential
|
||||
consistency*, where "the result of any execution is the same as if the
|
||||
operations of all the processors were executed in some sequential order,
|
||||
and the operations of each individual processor appear in this sequence
|
||||
in the order specified by its program".
|
||||
|
||||
qemu/atomic.h provides the following set of atomic read-modify-write
|
||||
operations:
|
||||
|
||||
void atomic_inc(ptr)
|
||||
void atomic_dec(ptr)
|
||||
void atomic_add(ptr, val)
|
||||
void atomic_sub(ptr, val)
|
||||
void atomic_and(ptr, val)
|
||||
void atomic_or(ptr, val)
|
||||
|
||||
typeof(*ptr) atomic_fetch_inc(ptr)
|
||||
typeof(*ptr) atomic_fetch_dec(ptr)
|
||||
typeof(*ptr) atomic_fetch_add(ptr, val)
|
||||
typeof(*ptr) atomic_fetch_sub(ptr, val)
|
||||
typeof(*ptr) atomic_fetch_and(ptr, val)
|
||||
typeof(*ptr) atomic_fetch_or(ptr, val)
|
||||
typeof(*ptr) atomic_xchg(ptr, val
|
||||
typeof(*ptr) atomic_cmpxchg(ptr, old, new)
|
||||
|
||||
all of which return the old value of *ptr. These operations are
|
||||
polymorphic; they operate on any type that is as wide as an int.
|
||||
|
||||
Sequentially consistent loads and stores can be done using:
|
||||
|
||||
atomic_fetch_add(ptr, 0) for loads
|
||||
atomic_xchg(ptr, val) for stores
|
||||
|
||||
However, they are quite expensive on some platforms, notably POWER and
|
||||
ARM. Therefore, qemu/atomic.h provides two primitives with slightly
|
||||
weaker constraints:
|
||||
|
||||
typeof(*ptr) atomic_mb_read(ptr)
|
||||
void atomic_mb_set(ptr, val)
|
||||
|
||||
The semantics of these primitives map to Java volatile variables,
|
||||
and are strongly related to memory barriers as used in the Linux
|
||||
kernel (see below).
|
||||
|
||||
As long as you use atomic_mb_read and atomic_mb_set, accesses cannot
|
||||
be reordered with each other, and it is also not possible to reorder
|
||||
"normal" accesses around them.
|
||||
|
||||
However, and this is the important difference between
|
||||
atomic_mb_read/atomic_mb_set and sequential consistency, it is important
|
||||
for both threads to access the same volatile variable. It is not the
|
||||
case that everything visible to thread A when it writes volatile field f
|
||||
becomes visible to thread B after it reads volatile field g. The store
|
||||
and load have to "match" (i.e., be performed on the same volatile
|
||||
field) to achieve the right semantics.
|
||||
|
||||
|
||||
These operations operate on any type that is as wide as an int or smaller.
|
||||
|
||||
|
||||
WEAK ATOMIC ACCESS AND MANUAL MEMORY BARRIERS
|
||||
=============================================
|
||||
|
||||
Compared to sequentially consistent atomic access, programming with
|
||||
weaker consistency models can be considerably more complicated.
|
||||
In general, if the algorithm you are writing includes both writes
|
||||
and reads on the same side, it is generally simpler to use sequentially
|
||||
consistent primitives.
|
||||
|
||||
When using this model, variables are accessed with atomic_read() and
|
||||
atomic_set(), and restrictions to the ordering of accesses is enforced
|
||||
using the smp_rmb(), smp_wmb(), smp_mb() and smp_read_barrier_depends()
|
||||
memory barriers.
|
||||
|
||||
atomic_read() and atomic_set() prevents the compiler from using
|
||||
optimizations that might otherwise optimize accesses out of existence
|
||||
on the one hand, or that might create unsolicited accesses on the other.
|
||||
In general this should not have any effect, because the same compiler
|
||||
barriers are already implied by memory barriers. However, it is useful
|
||||
to do so, because it tells readers which variables are shared with
|
||||
other threads, and which are local to the current thread or protected
|
||||
by other, more mundane means.
|
||||
|
||||
Memory barriers control the order of references to shared memory.
|
||||
They come in four kinds:
|
||||
|
||||
- smp_rmb() guarantees that all the LOAD operations specified before
|
||||
the barrier will appear to happen before all the LOAD operations
|
||||
specified after the barrier with respect to the other components of
|
||||
the system.
|
||||
|
||||
In other words, smp_rmb() puts a partial ordering on loads, but is not
|
||||
required to have any effect on stores.
|
||||
|
||||
- smp_wmb() guarantees that all the STORE operations specified before
|
||||
the barrier will appear to happen before all the STORE operations
|
||||
specified after the barrier with respect to the other components of
|
||||
the system.
|
||||
|
||||
In other words, smp_wmb() puts a partial ordering on stores, but is not
|
||||
required to have any effect on loads.
|
||||
|
||||
- smp_mb() guarantees that all the LOAD and STORE operations specified
|
||||
before the barrier will appear to happen before all the LOAD and
|
||||
STORE operations specified after the barrier with respect to the other
|
||||
components of the system.
|
||||
|
||||
smp_mb() puts a partial ordering on both loads and stores. It is
|
||||
stronger than both a read and a write memory barrier; it implies both
|
||||
smp_rmb() and smp_wmb(), but it also prevents STOREs coming before the
|
||||
barrier from overtaking LOADs coming after the barrier and vice versa.
|
||||
|
||||
- smp_read_barrier_depends() is a weaker kind of read barrier. On
|
||||
most processors, whenever two loads are performed such that the
|
||||
second depends on the result of the first (e.g., the first load
|
||||
retrieves the address to which the second load will be directed),
|
||||
the processor will guarantee that the first LOAD will appear to happen
|
||||
before the second with respect to the other components of the system.
|
||||
However, this is not always true---for example, it was not true on
|
||||
Alpha processors. Whenever this kind of access happens to shared
|
||||
memory (that is not protected by a lock), a read barrier is needed,
|
||||
and smp_read_barrier_depends() can be used instead of smp_rmb().
|
||||
|
||||
Note that the first load really has to have a _data_ dependency and not
|
||||
a control dependency. If the address for the second load is dependent
|
||||
on the first load, but the dependency is through a conditional rather
|
||||
than actually loading the address itself, then it's a _control_
|
||||
dependency and a full read barrier or better is required.
|
||||
|
||||
|
||||
This is the set of barriers that is required *between* two atomic_read()
|
||||
and atomic_set() operations to achieve sequential consistency:
|
||||
|
||||
| 2nd operation |
|
||||
|-----------------------------------------|
|
||||
1st operation | (after last) | atomic_read | atomic_set |
|
||||
---------------+--------------+-------------+------------|
|
||||
(before first) | | none | smp_wmb() |
|
||||
---------------+--------------+-------------+------------|
|
||||
atomic_read | smp_rmb() | smp_rmb()* | ** |
|
||||
---------------+--------------+-------------+------------|
|
||||
atomic_set | none | smp_mb()*** | smp_wmb() |
|
||||
---------------+--------------+-------------+------------|
|
||||
|
||||
* Or smp_read_barrier_depends().
|
||||
|
||||
** This requires a load-store barrier. How to achieve this varies
|
||||
depending on the machine, but in practice smp_rmb()+smp_wmb()
|
||||
should have the desired effect. For example, on PowerPC the
|
||||
lwsync instruction is a combined load-load, load-store and
|
||||
store-store barrier.
|
||||
|
||||
*** This requires a store-load barrier. On most machines, the only
|
||||
way to achieve this is a full barrier.
|
||||
|
||||
|
||||
You can see that the two possible definitions of atomic_mb_read()
|
||||
and atomic_mb_set() are the following:
|
||||
|
||||
1) atomic_mb_read(p) = atomic_read(p); smp_rmb()
|
||||
atomic_mb_set(p, v) = smp_wmb(); atomic_set(p, v); smp_mb()
|
||||
|
||||
2) atomic_mb_read(p) = smp_mb() atomic_read(p); smp_rmb()
|
||||
atomic_mb_set(p, v) = smp_wmb(); atomic_set(p, v);
|
||||
|
||||
Usually the former is used, because smp_mb() is expensive and a program
|
||||
normally has more reads than writes. Therefore it makes more sense to
|
||||
make atomic_mb_set() the more expensive operation.
|
||||
|
||||
There are two common cases in which atomic_mb_read and atomic_mb_set
|
||||
generate too many memory barriers, and thus it can be useful to manually
|
||||
place barriers instead:
|
||||
|
||||
- when a data structure has one thread that is always a writer
|
||||
and one thread that is always a reader, manual placement of
|
||||
memory barriers makes the write side faster. Furthermore,
|
||||
correctness is easy to check for in this case using the "pairing"
|
||||
trick that is explained below:
|
||||
|
||||
thread 1 thread 1
|
||||
------------------------- ------------------------
|
||||
(other writes)
|
||||
smp_wmb()
|
||||
atomic_mb_set(&a, x) atomic_set(&a, x)
|
||||
smp_wmb()
|
||||
atomic_mb_set(&b, y) atomic_set(&b, y)
|
||||
|
||||
=>
|
||||
thread 2 thread 2
|
||||
------------------------- ------------------------
|
||||
y = atomic_mb_read(&b) y = atomic_read(&b)
|
||||
smp_rmb()
|
||||
x = atomic_mb_read(&a) x = atomic_read(&a)
|
||||
smp_rmb()
|
||||
|
||||
- sometimes, a thread is accessing many variables that are otherwise
|
||||
unrelated to each other (for example because, apart from the current
|
||||
thread, exactly one other thread will read or write each of these
|
||||
variables). In this case, it is possible to "hoist" the implicit
|
||||
barriers provided by atomic_mb_read() and atomic_mb_set() outside
|
||||
a loop. For example, the above definition atomic_mb_read() gives
|
||||
the following transformation:
|
||||
|
||||
n = 0; n = 0;
|
||||
for (i = 0; i < 10; i++) => for (i = 0; i < 10; i++)
|
||||
n += atomic_mb_read(&a[i]); n += atomic_read(&a[i]);
|
||||
smp_rmb();
|
||||
|
||||
Similarly, atomic_mb_set() can be transformed as follows:
|
||||
smp_mb():
|
||||
|
||||
smp_wmb();
|
||||
for (i = 0; i < 10; i++) => for (i = 0; i < 10; i++)
|
||||
atomic_mb_set(&a[i], false); atomic_set(&a[i], false);
|
||||
smp_mb();
|
||||
|
||||
|
||||
The two tricks can be combined. In this case, splitting a loop in
|
||||
two lets you hoist the barriers out of the loops _and_ eliminate the
|
||||
expensive smp_mb():
|
||||
|
||||
smp_wmb();
|
||||
for (i = 0; i < 10; i++) { => for (i = 0; i < 10; i++)
|
||||
atomic_mb_set(&a[i], false); atomic_set(&a[i], false);
|
||||
atomic_mb_set(&b[i], false); smb_wmb();
|
||||
} for (i = 0; i < 10; i++)
|
||||
atomic_set(&a[i], false);
|
||||
smp_mb();
|
||||
|
||||
The other thread can still use atomic_mb_read()/atomic_mb_set()
|
||||
|
||||
|
||||
Memory barrier pairing
|
||||
----------------------
|
||||
|
||||
A useful rule of thumb is that memory barriers should always, or almost
|
||||
always, be paired with another barrier. In the case of QEMU, however,
|
||||
note that the other barrier may actually be in a driver that runs in
|
||||
the guest!
|
||||
|
||||
For the purposes of pairing, smp_read_barrier_depends() and smp_rmb()
|
||||
both count as read barriers. A read barriers shall pair with a write
|
||||
barrier or a full barrier; a write barrier shall pair with a read
|
||||
barrier or a full barrier. A full barrier can pair with anything.
|
||||
For example:
|
||||
|
||||
thread 1 thread 2
|
||||
=============== ===============
|
||||
a = 1;
|
||||
smp_wmb();
|
||||
b = 2; x = b;
|
||||
smp_rmb();
|
||||
y = a;
|
||||
|
||||
Note that the "writing" thread are accessing the variables in the
|
||||
opposite order as the "reading" thread. This is expected: stores
|
||||
before the write barrier will normally match the loads after the
|
||||
read barrier, and vice versa. The same is true for more than 2
|
||||
access and for data dependency barriers:
|
||||
|
||||
thread 1 thread 2
|
||||
=============== ===============
|
||||
b[2] = 1;
|
||||
smp_wmb();
|
||||
x->i = 2;
|
||||
smp_wmb();
|
||||
a = x; x = a;
|
||||
smp_read_barrier_depends();
|
||||
y = x->i;
|
||||
smp_read_barrier_depends();
|
||||
z = b[y];
|
||||
|
||||
smp_wmb() also pairs with atomic_mb_read(), and smp_rmb() also pairs
|
||||
with atomic_mb_set().
|
||||
|
||||
|
||||
COMPARISON WITH LINUX KERNEL MEMORY BARRIERS
|
||||
============================================
|
||||
|
||||
Here is a list of differences between Linux kernel atomic operations
|
||||
and memory barriers, and the equivalents in QEMU:
|
||||
|
||||
- atomic operations in Linux are always on a 32-bit int type and
|
||||
use a boxed atomic_t type; atomic operations in QEMU are polymorphic
|
||||
and use normal C types.
|
||||
|
||||
- atomic_read and atomic_set in Linux give no guarantee at all;
|
||||
atomic_read and atomic_set in QEMU include a compiler barrier
|
||||
(similar to the ACCESS_ONCE macro in Linux).
|
||||
|
||||
- most atomic read-modify-write operations in Linux return void;
|
||||
in QEMU, all of them return the old value of the variable.
|
||||
|
||||
- different atomic read-modify-write operations in Linux imply
|
||||
a different set of memory barriers; in QEMU, all of them enforce
|
||||
sequential consistency, which means they imply full memory barriers
|
||||
before and after the operation.
|
||||
|
||||
- Linux does not have an equivalent of atomic_mb_read() and
|
||||
atomic_mb_set(). In particular, note that set_mb() is a little
|
||||
weaker than atomic_mb_set().
|
||||
|
||||
|
||||
SOURCES
|
||||
=======
|
||||
|
||||
* Documentation/memory-barriers.txt from the Linux kernel
|
||||
|
||||
* "The JSR-133 Cookbook for Compiler Writers", available at
|
||||
http://g.oswego.edu/dl/jmm/cookbook.html
|
||||
427
exec.c
427
exec.c
|
|
@ -88,12 +88,15 @@ struct PhysPageEntry {
|
|||
uint16_t ptr : 15;
|
||||
};
|
||||
|
||||
typedef PhysPageEntry Node[L2_SIZE];
|
||||
|
||||
struct AddressSpaceDispatch {
|
||||
/* This is a multi-level map on the physical address space.
|
||||
* The bottom level has pointers to MemoryRegionSections.
|
||||
*/
|
||||
PhysPageEntry phys_map;
|
||||
MemoryListener listener;
|
||||
Node *nodes;
|
||||
MemoryRegionSection *sections;
|
||||
AddressSpace *as;
|
||||
};
|
||||
|
||||
|
|
@ -105,16 +108,22 @@ typedef struct subpage_t {
|
|||
uint16_t sub_section[TARGET_PAGE_SIZE];
|
||||
} subpage_t;
|
||||
|
||||
static MemoryRegionSection *phys_sections;
|
||||
static unsigned phys_sections_nb, phys_sections_nb_alloc;
|
||||
static uint16_t phys_section_unassigned;
|
||||
static uint16_t phys_section_notdirty;
|
||||
static uint16_t phys_section_rom;
|
||||
static uint16_t phys_section_watch;
|
||||
#define PHYS_SECTION_UNASSIGNED 0
|
||||
#define PHYS_SECTION_NOTDIRTY 1
|
||||
#define PHYS_SECTION_ROM 2
|
||||
#define PHYS_SECTION_WATCH 3
|
||||
|
||||
/* Simple allocator for PhysPageEntry nodes */
|
||||
static PhysPageEntry (*phys_map_nodes)[L2_SIZE];
|
||||
static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc;
|
||||
typedef struct PhysPageMap {
|
||||
unsigned sections_nb;
|
||||
unsigned sections_nb_alloc;
|
||||
unsigned nodes_nb;
|
||||
unsigned nodes_nb_alloc;
|
||||
Node *nodes;
|
||||
MemoryRegionSection *sections;
|
||||
} PhysPageMap;
|
||||
|
||||
static PhysPageMap *prev_map;
|
||||
static PhysPageMap next_map;
|
||||
|
||||
#define PHYS_MAP_NODE_NIL (((uint16_t)~0) >> 1)
|
||||
|
||||
|
|
@ -129,13 +138,13 @@ static MemoryRegion io_mem_watch;
|
|||
|
||||
static void phys_map_node_reserve(unsigned nodes)
|
||||
{
|
||||
if (phys_map_nodes_nb + nodes > phys_map_nodes_nb_alloc) {
|
||||
typedef PhysPageEntry Node[L2_SIZE];
|
||||
phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc * 2, 16);
|
||||
phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc,
|
||||
phys_map_nodes_nb + nodes);
|
||||
phys_map_nodes = g_renew(Node, phys_map_nodes,
|
||||
phys_map_nodes_nb_alloc);
|
||||
if (next_map.nodes_nb + nodes > next_map.nodes_nb_alloc) {
|
||||
next_map.nodes_nb_alloc = MAX(next_map.nodes_nb_alloc * 2,
|
||||
16);
|
||||
next_map.nodes_nb_alloc = MAX(next_map.nodes_nb_alloc,
|
||||
next_map.nodes_nb + nodes);
|
||||
next_map.nodes = g_renew(Node, next_map.nodes,
|
||||
next_map.nodes_nb_alloc);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -144,22 +153,16 @@ static uint16_t phys_map_node_alloc(void)
|
|||
unsigned i;
|
||||
uint16_t ret;
|
||||
|
||||
ret = phys_map_nodes_nb++;
|
||||
ret = next_map.nodes_nb++;
|
||||
assert(ret != PHYS_MAP_NODE_NIL);
|
||||
assert(ret != phys_map_nodes_nb_alloc);
|
||||
assert(ret != next_map.nodes_nb_alloc);
|
||||
for (i = 0; i < L2_SIZE; ++i) {
|
||||
phys_map_nodes[ret][i].is_leaf = 0;
|
||||
phys_map_nodes[ret][i].ptr = PHYS_MAP_NODE_NIL;
|
||||
next_map.nodes[ret][i].is_leaf = 0;
|
||||
next_map.nodes[ret][i].ptr = PHYS_MAP_NODE_NIL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void phys_map_nodes_reset(void)
|
||||
{
|
||||
phys_map_nodes_nb = 0;
|
||||
}
|
||||
|
||||
|
||||
static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
|
||||
hwaddr *nb, uint16_t leaf,
|
||||
int level)
|
||||
|
|
@ -170,15 +173,15 @@ static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
|
|||
|
||||
if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
|
||||
lp->ptr = phys_map_node_alloc();
|
||||
p = phys_map_nodes[lp->ptr];
|
||||
p = next_map.nodes[lp->ptr];
|
||||
if (level == 0) {
|
||||
for (i = 0; i < L2_SIZE; i++) {
|
||||
p[i].is_leaf = 1;
|
||||
p[i].ptr = phys_section_unassigned;
|
||||
p[i].ptr = PHYS_SECTION_UNASSIGNED;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
p = phys_map_nodes[lp->ptr];
|
||||
p = next_map.nodes[lp->ptr];
|
||||
}
|
||||
lp = &p[(*index >> (level * L2_BITS)) & (L2_SIZE - 1)];
|
||||
|
||||
|
|
@ -205,20 +208,20 @@ static void phys_page_set(AddressSpaceDispatch *d,
|
|||
phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
|
||||
}
|
||||
|
||||
static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
|
||||
static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr index,
|
||||
Node *nodes, MemoryRegionSection *sections)
|
||||
{
|
||||
PhysPageEntry lp = d->phys_map;
|
||||
PhysPageEntry *p;
|
||||
int i;
|
||||
|
||||
for (i = P_L2_LEVELS - 1; i >= 0 && !lp.is_leaf; i--) {
|
||||
if (lp.ptr == PHYS_MAP_NODE_NIL) {
|
||||
return &phys_sections[phys_section_unassigned];
|
||||
return §ions[PHYS_SECTION_UNASSIGNED];
|
||||
}
|
||||
p = phys_map_nodes[lp.ptr];
|
||||
p = nodes[lp.ptr];
|
||||
lp = p[(index >> (i * L2_BITS)) & (L2_SIZE - 1)];
|
||||
}
|
||||
return &phys_sections[lp.ptr];
|
||||
return §ions[lp.ptr];
|
||||
}
|
||||
|
||||
bool memory_region_is_unassigned(MemoryRegion *mr)
|
||||
|
|
@ -227,29 +230,30 @@ bool memory_region_is_unassigned(MemoryRegion *mr)
|
|||
&& mr != &io_mem_watch;
|
||||
}
|
||||
|
||||
static MemoryRegionSection *address_space_lookup_region(AddressSpace *as,
|
||||
static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
|
||||
hwaddr addr,
|
||||
bool resolve_subpage)
|
||||
{
|
||||
MemoryRegionSection *section;
|
||||
subpage_t *subpage;
|
||||
|
||||
section = phys_page_find(as->dispatch, addr >> TARGET_PAGE_BITS);
|
||||
section = phys_page_find(d->phys_map, addr >> TARGET_PAGE_BITS,
|
||||
d->nodes, d->sections);
|
||||
if (resolve_subpage && section->mr->subpage) {
|
||||
subpage = container_of(section->mr, subpage_t, iomem);
|
||||
section = &phys_sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
|
||||
section = &d->sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
|
||||
}
|
||||
return section;
|
||||
}
|
||||
|
||||
static MemoryRegionSection *
|
||||
address_space_translate_internal(AddressSpace *as, hwaddr addr, hwaddr *xlat,
|
||||
address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
|
||||
hwaddr *plen, bool resolve_subpage)
|
||||
{
|
||||
MemoryRegionSection *section;
|
||||
Int128 diff;
|
||||
|
||||
section = address_space_lookup_region(as, addr, resolve_subpage);
|
||||
section = address_space_lookup_region(d, addr, resolve_subpage);
|
||||
/* Compute offset within MemoryRegionSection */
|
||||
addr -= section->offset_within_address_space;
|
||||
|
||||
|
|
@ -271,7 +275,7 @@ MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
|
|||
hwaddr len = *plen;
|
||||
|
||||
for (;;) {
|
||||
section = address_space_translate_internal(as, addr, &addr, plen, true);
|
||||
section = address_space_translate_internal(as->dispatch, addr, &addr, plen, true);
|
||||
mr = section->mr;
|
||||
|
||||
if (!mr->iommu_ops) {
|
||||
|
|
@ -300,7 +304,7 @@ address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
|
|||
hwaddr *plen)
|
||||
{
|
||||
MemoryRegionSection *section;
|
||||
section = address_space_translate_internal(as, addr, xlat, plen, false);
|
||||
section = address_space_translate_internal(as->dispatch, addr, xlat, plen, false);
|
||||
|
||||
assert(!section->mr->iommu_ops);
|
||||
return section;
|
||||
|
|
@ -723,12 +727,12 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
|
|||
iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
|
||||
+ xlat;
|
||||
if (!section->readonly) {
|
||||
iotlb |= phys_section_notdirty;
|
||||
iotlb |= PHYS_SECTION_NOTDIRTY;
|
||||
} else {
|
||||
iotlb |= phys_section_rom;
|
||||
iotlb |= PHYS_SECTION_ROM;
|
||||
}
|
||||
} else {
|
||||
iotlb = section - phys_sections;
|
||||
iotlb = section - address_space_memory.dispatch->sections;
|
||||
iotlb += xlat;
|
||||
}
|
||||
|
||||
|
|
@ -738,7 +742,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
|
|||
if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
|
||||
/* Avoid trapping reads of pages with a write breakpoint. */
|
||||
if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
|
||||
iotlb = phys_section_watch + paddr;
|
||||
iotlb = PHYS_SECTION_WATCH + paddr;
|
||||
*address |= TLB_MMIO;
|
||||
break;
|
||||
}
|
||||
|
|
@ -754,10 +758,29 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
|
|||
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
||||
uint16_t section);
|
||||
static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
|
||||
static void destroy_page_desc(uint16_t section_index)
|
||||
|
||||
static uint16_t phys_section_add(MemoryRegionSection *section)
|
||||
{
|
||||
MemoryRegionSection *section = &phys_sections[section_index];
|
||||
MemoryRegion *mr = section->mr;
|
||||
/* The physical section number is ORed with a page-aligned
|
||||
* pointer to produce the iotlb entries. Thus it should
|
||||
* never overflow into the page-aligned value.
|
||||
*/
|
||||
assert(next_map.sections_nb < TARGET_PAGE_SIZE);
|
||||
|
||||
if (next_map.sections_nb == next_map.sections_nb_alloc) {
|
||||
next_map.sections_nb_alloc = MAX(next_map.sections_nb_alloc * 2,
|
||||
16);
|
||||
next_map.sections = g_renew(MemoryRegionSection, next_map.sections,
|
||||
next_map.sections_nb_alloc);
|
||||
}
|
||||
next_map.sections[next_map.sections_nb] = *section;
|
||||
memory_region_ref(section->mr);
|
||||
return next_map.sections_nb++;
|
||||
}
|
||||
|
||||
static void phys_section_destroy(MemoryRegion *mr)
|
||||
{
|
||||
memory_region_unref(mr);
|
||||
|
||||
if (mr->subpage) {
|
||||
subpage_t *subpage = container_of(mr, subpage_t, iomem);
|
||||
|
|
@ -766,53 +789,15 @@ static void destroy_page_desc(uint16_t section_index)
|
|||
}
|
||||
}
|
||||
|
||||
static void destroy_l2_mapping(PhysPageEntry *lp, unsigned level)
|
||||
static void phys_sections_free(PhysPageMap *map)
|
||||
{
|
||||
unsigned i;
|
||||
PhysPageEntry *p;
|
||||
|
||||
if (lp->ptr == PHYS_MAP_NODE_NIL) {
|
||||
return;
|
||||
while (map->sections_nb > 0) {
|
||||
MemoryRegionSection *section = &map->sections[--map->sections_nb];
|
||||
phys_section_destroy(section->mr);
|
||||
}
|
||||
|
||||
p = phys_map_nodes[lp->ptr];
|
||||
for (i = 0; i < L2_SIZE; ++i) {
|
||||
if (!p[i].is_leaf) {
|
||||
destroy_l2_mapping(&p[i], level - 1);
|
||||
} else {
|
||||
destroy_page_desc(p[i].ptr);
|
||||
}
|
||||
}
|
||||
lp->is_leaf = 0;
|
||||
lp->ptr = PHYS_MAP_NODE_NIL;
|
||||
}
|
||||
|
||||
static void destroy_all_mappings(AddressSpaceDispatch *d)
|
||||
{
|
||||
destroy_l2_mapping(&d->phys_map, P_L2_LEVELS - 1);
|
||||
phys_map_nodes_reset();
|
||||
}
|
||||
|
||||
static uint16_t phys_section_add(MemoryRegionSection *section)
|
||||
{
|
||||
/* The physical section number is ORed with a page-aligned
|
||||
* pointer to produce the iotlb entries. Thus it should
|
||||
* never overflow into the page-aligned value.
|
||||
*/
|
||||
assert(phys_sections_nb < TARGET_PAGE_SIZE);
|
||||
|
||||
if (phys_sections_nb == phys_sections_nb_alloc) {
|
||||
phys_sections_nb_alloc = MAX(phys_sections_nb_alloc * 2, 16);
|
||||
phys_sections = g_renew(MemoryRegionSection, phys_sections,
|
||||
phys_sections_nb_alloc);
|
||||
}
|
||||
phys_sections[phys_sections_nb] = *section;
|
||||
return phys_sections_nb++;
|
||||
}
|
||||
|
||||
static void phys_sections_clear(void)
|
||||
{
|
||||
phys_sections_nb = 0;
|
||||
g_free(map->sections);
|
||||
g_free(map->nodes);
|
||||
g_free(map);
|
||||
}
|
||||
|
||||
static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
|
||||
|
|
@ -820,7 +805,8 @@ static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *secti
|
|||
subpage_t *subpage;
|
||||
hwaddr base = section->offset_within_address_space
|
||||
& TARGET_PAGE_MASK;
|
||||
MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
|
||||
MemoryRegionSection *existing = phys_page_find(d->phys_map, base >> TARGET_PAGE_BITS,
|
||||
next_map.nodes, next_map.sections);
|
||||
MemoryRegionSection subsection = {
|
||||
.offset_within_address_space = base,
|
||||
.size = int128_make64(TARGET_PAGE_SIZE),
|
||||
|
|
@ -857,7 +843,8 @@ static void register_multipage(AddressSpaceDispatch *d,
|
|||
|
||||
static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
|
||||
{
|
||||
AddressSpaceDispatch *d = container_of(listener, AddressSpaceDispatch, listener);
|
||||
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
|
||||
AddressSpaceDispatch *d = as->next_dispatch;
|
||||
MemoryRegionSection now = *section, remain = *section;
|
||||
Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
|
||||
|
||||
|
|
@ -1316,15 +1303,7 @@ void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
|
|||
}
|
||||
#endif /* !_WIN32 */
|
||||
|
||||
/* Return a host pointer to ram allocated with qemu_ram_alloc.
|
||||
With the exception of the softmmu code in this file, this should
|
||||
only be used for local memory (e.g. video ram) that the device owns,
|
||||
and knows it isn't going to access beyond the end of the block.
|
||||
|
||||
It should not be used for general purpose DMA.
|
||||
Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
|
||||
*/
|
||||
void *qemu_get_ram_ptr(ram_addr_t addr)
|
||||
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
|
||||
{
|
||||
RAMBlock *block;
|
||||
|
||||
|
|
@ -1344,6 +1323,21 @@ void *qemu_get_ram_ptr(ram_addr_t addr)
|
|||
|
||||
found:
|
||||
ram_list.mru_block = block;
|
||||
return block;
|
||||
}
|
||||
|
||||
/* Return a host pointer to ram allocated with qemu_ram_alloc.
|
||||
With the exception of the softmmu code in this file, this should
|
||||
only be used for local memory (e.g. video ram) that the device owns,
|
||||
and knows it isn't going to access beyond the end of the block.
|
||||
|
||||
It should not be used for general purpose DMA.
|
||||
Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
|
||||
*/
|
||||
void *qemu_get_ram_ptr(ram_addr_t addr)
|
||||
{
|
||||
RAMBlock *block = qemu_get_ram_block(addr);
|
||||
|
||||
if (xen_enabled()) {
|
||||
/* We need to check if the requested address is in the RAM
|
||||
* because we don't want to map the entire memory in QEMU.
|
||||
|
|
@ -1418,14 +1412,21 @@ static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size)
|
|||
}
|
||||
}
|
||||
|
||||
int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
|
||||
/* Some of the softmmu routines need to translate from a host pointer
|
||||
(typically a TLB entry) back to a ram offset. */
|
||||
MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
|
||||
{
|
||||
RAMBlock *block;
|
||||
uint8_t *host = ptr;
|
||||
|
||||
if (xen_enabled()) {
|
||||
*ram_addr = xen_ram_addr_from_mapcache(ptr);
|
||||
return 0;
|
||||
return qemu_get_ram_block(*ram_addr)->mr;
|
||||
}
|
||||
|
||||
block = ram_list.mru_block;
|
||||
if (block && block->host && host - block->host < block->length) {
|
||||
goto found;
|
||||
}
|
||||
|
||||
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
||||
|
|
@ -1434,25 +1435,15 @@ int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
|
|||
continue;
|
||||
}
|
||||
if (host - block->host < block->length) {
|
||||
*ram_addr = block->offset + (host - block->host);
|
||||
return 0;
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
return NULL;
|
||||
|
||||
/* Some of the softmmu routines need to translate from a host pointer
|
||||
(typically a TLB entry) back to a ram offset. */
|
||||
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
|
||||
{
|
||||
ram_addr_t ram_addr;
|
||||
|
||||
if (qemu_ram_addr_from_host(ptr, &ram_addr)) {
|
||||
fprintf(stderr, "Bad ram pointer %p\n", ptr);
|
||||
abort();
|
||||
}
|
||||
return ram_addr;
|
||||
found:
|
||||
*ram_addr = block->offset + (host - block->host);
|
||||
return block->mr;
|
||||
}
|
||||
|
||||
static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
|
||||
|
|
@ -1673,14 +1664,14 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
|
|||
|
||||
mmio->as = as;
|
||||
mmio->base = base;
|
||||
memory_region_init_io(&mmio->iomem, &subpage_ops, mmio,
|
||||
memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
|
||||
"subpage", TARGET_PAGE_SIZE);
|
||||
mmio->iomem.subpage = true;
|
||||
#if defined(DEBUG_SUBPAGE)
|
||||
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
|
||||
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
|
||||
#endif
|
||||
subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, phys_section_unassigned);
|
||||
subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
|
||||
|
||||
return mmio;
|
||||
}
|
||||
|
|
@ -1699,35 +1690,67 @@ static uint16_t dummy_section(MemoryRegion *mr)
|
|||
|
||||
MemoryRegion *iotlb_to_region(hwaddr index)
|
||||
{
|
||||
return phys_sections[index & ~TARGET_PAGE_MASK].mr;
|
||||
return address_space_memory.dispatch->sections[index & ~TARGET_PAGE_MASK].mr;
|
||||
}
|
||||
|
||||
static void io_mem_init(void)
|
||||
{
|
||||
memory_region_init_io(&io_mem_rom, &unassigned_mem_ops, NULL, "rom", UINT64_MAX);
|
||||
memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL,
|
||||
memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, "rom", UINT64_MAX);
|
||||
memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
|
||||
"unassigned", UINT64_MAX);
|
||||
memory_region_init_io(&io_mem_notdirty, ¬dirty_mem_ops, NULL,
|
||||
memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL,
|
||||
"notdirty", UINT64_MAX);
|
||||
memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL,
|
||||
memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
|
||||
"watch", UINT64_MAX);
|
||||
}
|
||||
|
||||
static void mem_begin(MemoryListener *listener)
|
||||
{
|
||||
AddressSpaceDispatch *d = container_of(listener, AddressSpaceDispatch, listener);
|
||||
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
|
||||
AddressSpaceDispatch *d = g_new(AddressSpaceDispatch, 1);
|
||||
|
||||
destroy_all_mappings(d);
|
||||
d->phys_map.ptr = PHYS_MAP_NODE_NIL;
|
||||
d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .is_leaf = 0 };
|
||||
d->as = as;
|
||||
as->next_dispatch = d;
|
||||
}
|
||||
|
||||
static void mem_commit(MemoryListener *listener)
|
||||
{
|
||||
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
|
||||
AddressSpaceDispatch *cur = as->dispatch;
|
||||
AddressSpaceDispatch *next = as->next_dispatch;
|
||||
|
||||
next->nodes = next_map.nodes;
|
||||
next->sections = next_map.sections;
|
||||
|
||||
as->dispatch = next;
|
||||
g_free(cur);
|
||||
}
|
||||
|
||||
static void core_begin(MemoryListener *listener)
|
||||
{
|
||||
phys_sections_clear();
|
||||
phys_section_unassigned = dummy_section(&io_mem_unassigned);
|
||||
phys_section_notdirty = dummy_section(&io_mem_notdirty);
|
||||
phys_section_rom = dummy_section(&io_mem_rom);
|
||||
phys_section_watch = dummy_section(&io_mem_watch);
|
||||
uint16_t n;
|
||||
|
||||
prev_map = g_new(PhysPageMap, 1);
|
||||
*prev_map = next_map;
|
||||
|
||||
memset(&next_map, 0, sizeof(next_map));
|
||||
n = dummy_section(&io_mem_unassigned);
|
||||
assert(n == PHYS_SECTION_UNASSIGNED);
|
||||
n = dummy_section(&io_mem_notdirty);
|
||||
assert(n == PHYS_SECTION_NOTDIRTY);
|
||||
n = dummy_section(&io_mem_rom);
|
||||
assert(n == PHYS_SECTION_ROM);
|
||||
n = dummy_section(&io_mem_watch);
|
||||
assert(n == PHYS_SECTION_WATCH);
|
||||
}
|
||||
|
||||
/* This listener's commit run after the other AddressSpaceDispatch listeners'.
|
||||
* All AddressSpaceDispatch instances have switched to the next map.
|
||||
*/
|
||||
static void core_commit(MemoryListener *listener)
|
||||
{
|
||||
phys_sections_free(prev_map);
|
||||
}
|
||||
|
||||
static void tcg_commit(MemoryListener *listener)
|
||||
|
|
@ -1752,65 +1775,36 @@ static void core_log_global_stop(MemoryListener *listener)
|
|||
cpu_physical_memory_set_dirty_tracking(0);
|
||||
}
|
||||
|
||||
static void io_region_add(MemoryListener *listener,
|
||||
MemoryRegionSection *section)
|
||||
{
|
||||
MemoryRegionIORange *mrio = g_new(MemoryRegionIORange, 1);
|
||||
|
||||
mrio->mr = section->mr;
|
||||
mrio->offset = section->offset_within_region;
|
||||
iorange_init(&mrio->iorange, &memory_region_iorange_ops,
|
||||
section->offset_within_address_space,
|
||||
int128_get64(section->size));
|
||||
ioport_register(&mrio->iorange);
|
||||
}
|
||||
|
||||
static void io_region_del(MemoryListener *listener,
|
||||
MemoryRegionSection *section)
|
||||
{
|
||||
isa_unassign_ioport(section->offset_within_address_space,
|
||||
int128_get64(section->size));
|
||||
}
|
||||
|
||||
static MemoryListener core_memory_listener = {
|
||||
.begin = core_begin,
|
||||
.commit = core_commit,
|
||||
.log_global_start = core_log_global_start,
|
||||
.log_global_stop = core_log_global_stop,
|
||||
.priority = 1,
|
||||
};
|
||||
|
||||
static MemoryListener io_memory_listener = {
|
||||
.region_add = io_region_add,
|
||||
.region_del = io_region_del,
|
||||
.priority = 0,
|
||||
};
|
||||
|
||||
static MemoryListener tcg_memory_listener = {
|
||||
.commit = tcg_commit,
|
||||
};
|
||||
|
||||
void address_space_init_dispatch(AddressSpace *as)
|
||||
{
|
||||
AddressSpaceDispatch *d = g_new(AddressSpaceDispatch, 1);
|
||||
|
||||
d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .is_leaf = 0 };
|
||||
d->listener = (MemoryListener) {
|
||||
as->dispatch = NULL;
|
||||
as->dispatch_listener = (MemoryListener) {
|
||||
.begin = mem_begin,
|
||||
.commit = mem_commit,
|
||||
.region_add = mem_add,
|
||||
.region_nop = mem_add,
|
||||
.priority = 0,
|
||||
};
|
||||
d->as = as;
|
||||
as->dispatch = d;
|
||||
memory_listener_register(&d->listener, as);
|
||||
memory_listener_register(&as->dispatch_listener, as);
|
||||
}
|
||||
|
||||
void address_space_destroy_dispatch(AddressSpace *as)
|
||||
{
|
||||
AddressSpaceDispatch *d = as->dispatch;
|
||||
|
||||
memory_listener_unregister(&d->listener);
|
||||
destroy_l2_mapping(&d->phys_map, P_L2_LEVELS - 1);
|
||||
memory_listener_unregister(&as->dispatch_listener);
|
||||
g_free(d);
|
||||
as->dispatch = NULL;
|
||||
}
|
||||
|
|
@ -1818,15 +1812,14 @@ void address_space_destroy_dispatch(AddressSpace *as)
|
|||
static void memory_map_init(void)
|
||||
{
|
||||
system_memory = g_malloc(sizeof(*system_memory));
|
||||
memory_region_init(system_memory, "system", INT64_MAX);
|
||||
memory_region_init(system_memory, NULL, "system", INT64_MAX);
|
||||
address_space_init(&address_space_memory, system_memory, "memory");
|
||||
|
||||
system_io = g_malloc(sizeof(*system_io));
|
||||
memory_region_init(system_io, "io", 65536);
|
||||
memory_region_init(system_io, NULL, "io", 65536);
|
||||
address_space_init(&address_space_io, system_io, "I/O");
|
||||
|
||||
memory_listener_register(&core_memory_listener, &address_space_memory);
|
||||
memory_listener_register(&io_memory_listener, &address_space_io);
|
||||
memory_listener_register(&tcg_memory_listener, &address_space_memory);
|
||||
}
|
||||
|
||||
|
|
@ -2039,6 +2032,7 @@ void cpu_physical_memory_write_rom(hwaddr addr,
|
|||
}
|
||||
|
||||
typedef struct {
|
||||
MemoryRegion *mr;
|
||||
void *buffer;
|
||||
hwaddr addr;
|
||||
hwaddr len;
|
||||
|
|
@ -2118,47 +2112,56 @@ void *address_space_map(AddressSpace *as,
|
|||
bool is_write)
|
||||
{
|
||||
hwaddr len = *plen;
|
||||
hwaddr todo = 0;
|
||||
hwaddr l, xlat;
|
||||
MemoryRegion *mr;
|
||||
ram_addr_t raddr = RAM_ADDR_MAX;
|
||||
ram_addr_t rlen;
|
||||
void *ret;
|
||||
hwaddr done = 0;
|
||||
hwaddr l, xlat, base;
|
||||
MemoryRegion *mr, *this_mr;
|
||||
ram_addr_t raddr;
|
||||
|
||||
while (len > 0) {
|
||||
l = len;
|
||||
mr = address_space_translate(as, addr, &xlat, &l, is_write);
|
||||
if (len == 0) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (!memory_access_is_direct(mr, is_write)) {
|
||||
if (todo || bounce.buffer) {
|
||||
break;
|
||||
}
|
||||
bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
|
||||
bounce.addr = addr;
|
||||
bounce.len = l;
|
||||
if (!is_write) {
|
||||
address_space_read(as, addr, bounce.buffer, l);
|
||||
}
|
||||
|
||||
*plen = l;
|
||||
return bounce.buffer;
|
||||
l = len;
|
||||
mr = address_space_translate(as, addr, &xlat, &l, is_write);
|
||||
if (!memory_access_is_direct(mr, is_write)) {
|
||||
if (bounce.buffer) {
|
||||
return NULL;
|
||||
}
|
||||
if (!todo) {
|
||||
raddr = memory_region_get_ram_addr(mr) + xlat;
|
||||
} else {
|
||||
if (memory_region_get_ram_addr(mr) + xlat != raddr + todo) {
|
||||
break;
|
||||
}
|
||||
bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
|
||||
bounce.addr = addr;
|
||||
bounce.len = l;
|
||||
|
||||
memory_region_ref(mr);
|
||||
bounce.mr = mr;
|
||||
if (!is_write) {
|
||||
address_space_read(as, addr, bounce.buffer, l);
|
||||
}
|
||||
|
||||
*plen = l;
|
||||
return bounce.buffer;
|
||||
}
|
||||
|
||||
base = xlat;
|
||||
raddr = memory_region_get_ram_addr(mr);
|
||||
|
||||
for (;;) {
|
||||
len -= l;
|
||||
addr += l;
|
||||
todo += l;
|
||||
done += l;
|
||||
if (len == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
l = len;
|
||||
this_mr = address_space_translate(as, addr, &xlat, &l, is_write);
|
||||
if (this_mr != mr || xlat != base + done) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
rlen = todo;
|
||||
ret = qemu_ram_ptr_length(raddr, &rlen);
|
||||
*plen = rlen;
|
||||
return ret;
|
||||
|
||||
memory_region_ref(mr);
|
||||
*plen = done;
|
||||
return qemu_ram_ptr_length(raddr + base, plen);
|
||||
}
|
||||
|
||||
/* Unmaps a memory region previously mapped by address_space_map().
|
||||
|
|
@ -2169,8 +2172,12 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
|
|||
int is_write, hwaddr access_len)
|
||||
{
|
||||
if (buffer != bounce.buffer) {
|
||||
MemoryRegion *mr;
|
||||
ram_addr_t addr1;
|
||||
|
||||
mr = qemu_ram_addr_from_host(buffer, &addr1);
|
||||
assert(mr != NULL);
|
||||
if (is_write) {
|
||||
ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer);
|
||||
while (access_len) {
|
||||
unsigned l;
|
||||
l = TARGET_PAGE_SIZE;
|
||||
|
|
@ -2184,6 +2191,7 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
|
|||
if (xen_enabled()) {
|
||||
xen_invalidate_map_cache_entry(buffer);
|
||||
}
|
||||
memory_region_unref(mr);
|
||||
return;
|
||||
}
|
||||
if (is_write) {
|
||||
|
|
@ -2191,6 +2199,7 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
|
|||
}
|
||||
qemu_vfree(bounce.buffer);
|
||||
bounce.buffer = NULL;
|
||||
memory_region_unref(bounce.mr);
|
||||
cpu_notify_map_clients();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -419,7 +419,8 @@ void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
|
|||
MemoryRegion *parent)
|
||||
{
|
||||
ar->pm1.evt.update_sci = update_sci;
|
||||
memory_region_init_io(&ar->pm1.evt.io, &acpi_pm_evt_ops, ar, "acpi-evt", 4);
|
||||
memory_region_init_io(&ar->pm1.evt.io, memory_region_owner(parent),
|
||||
&acpi_pm_evt_ops, ar, "acpi-evt", 4);
|
||||
memory_region_add_subregion(parent, 0, &ar->pm1.evt.io);
|
||||
}
|
||||
|
||||
|
|
@ -481,7 +482,8 @@ void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
|
|||
{
|
||||
ar->tmr.update_sci = update_sci;
|
||||
ar->tmr.timer = qemu_new_timer_ns(vm_clock, acpi_pm_tmr_timer, ar);
|
||||
memory_region_init_io(&ar->tmr.io, &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
|
||||
memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),
|
||||
&acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
|
||||
memory_region_add_subregion(parent, 8, &ar->tmr.io);
|
||||
}
|
||||
|
||||
|
|
@ -552,7 +554,8 @@ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, uint8_t s4_val)
|
|||
ar->pm1.cnt.s4_val = s4_val;
|
||||
ar->wakeup.notify = acpi_notify_wakeup;
|
||||
qemu_register_wakeup_notifier(&ar->wakeup);
|
||||
memory_region_init_io(&ar->pm1.cnt.io, &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);
|
||||
memory_region_init_io(&ar->pm1.cnt.io, memory_region_owner(parent),
|
||||
&acpi_pm_cnt_ops, ar, "acpi-cnt", 2);
|
||||
memory_region_add_subregion(parent, 4, &ar->pm1.cnt.io);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -205,7 +205,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
|
|||
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
|
||||
qemu_irq sci_irq)
|
||||
{
|
||||
memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE);
|
||||
memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
|
||||
memory_region_set_enabled(&pm->io, false);
|
||||
memory_region_add_subregion(pci_address_space_io(lpc_pci),
|
||||
0, &pm->io);
|
||||
|
|
@ -215,12 +215,12 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
|
|||
acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2);
|
||||
|
||||
acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
|
||||
memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0",
|
||||
ICH9_PMIO_GPE0_LEN);
|
||||
memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
|
||||
"apci-gpe0", ICH9_PMIO_GPE0_LEN);
|
||||
memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
|
||||
|
||||
memory_region_init_io(&pm->io_smi, &ich9_smi_ops, pm, "apci-smi",
|
||||
8);
|
||||
memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
|
||||
"apci-smi", 8);
|
||||
memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
|
||||
|
||||
pm->irq = sci_irq;
|
||||
|
|
|
|||
|
|
@ -383,14 +383,15 @@ static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
|
|||
static void piix4_pm_machine_ready(Notifier *n, void *opaque)
|
||||
{
|
||||
PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
|
||||
MemoryRegion *io_as = pci_address_space_io(&s->dev);
|
||||
uint8_t *pci_conf;
|
||||
|
||||
pci_conf = s->dev.config;
|
||||
pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
|
||||
pci_conf[0x5f] = 0x10 |
|
||||
(memory_region_present(io_as, 0x378) ? 0x80 : 0);
|
||||
pci_conf[0x63] = 0x60;
|
||||
pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
|
||||
(isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
|
||||
|
||||
pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
|
||||
(memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
|
||||
}
|
||||
|
||||
static int piix4_pm_initfn(PCIDevice *dev)
|
||||
|
|
@ -423,7 +424,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
|
|||
memory_region_add_subregion(pci_address_space_io(dev),
|
||||
s->smb_io_base, &s->smb.io);
|
||||
|
||||
memory_region_init(&s->io, "piix4-pm", 64);
|
||||
memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
|
||||
memory_region_set_enabled(&s->io, false);
|
||||
memory_region_add_subregion(pci_address_space_io(dev),
|
||||
0, &s->io);
|
||||
|
|
@ -670,19 +671,19 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
|
|||
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
|
||||
PCIBus *bus, PIIX4PMState *s)
|
||||
{
|
||||
memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0",
|
||||
GPE_LEN);
|
||||
memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
|
||||
"acpi-gpe0", GPE_LEN);
|
||||
memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
|
||||
|
||||
memory_region_init_io(&s->io_pci, &piix4_pci_ops, s, "apci-pci-hotplug",
|
||||
PCI_HOTPLUG_SIZE);
|
||||
memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,
|
||||
"acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
|
||||
memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
|
||||
&s->io_pci);
|
||||
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
|
||||
|
||||
qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu);
|
||||
memory_region_init_io(&s->io_cpu, &cpu_hotplug_ops, s, "apci-cpu-hotplug",
|
||||
PIIX4_PROC_LEN);
|
||||
memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s,
|
||||
"acpi-cpu-hotplug", PIIX4_PROC_LEN);
|
||||
memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu);
|
||||
s->cpu_added_notifier.notify = piix4_cpu_added_req;
|
||||
qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
|
||||
|
|
|
|||
|
|
@ -741,7 +741,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
|
|||
|
||||
/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
|
||||
but the address space hole reserved at this point is 8TB. */
|
||||
memory_region_init_ram(&s->ram_region, "ram", ram_size);
|
||||
memory_region_init_ram(&s->ram_region, OBJECT(s), "ram", ram_size);
|
||||
vmstate_register_ram_global(&s->ram_region);
|
||||
memory_region_add_subregion(addr_space, 0, &s->ram_region);
|
||||
|
||||
|
|
@ -750,22 +750,25 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
|
|||
the flash ROM. I'm not sure that we need to implement it at all. */
|
||||
|
||||
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
|
||||
memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB);
|
||||
memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",
|
||||
256*MB);
|
||||
memory_region_add_subregion(addr_space, 0x80180000000ULL,
|
||||
&s->pchip.region);
|
||||
|
||||
/* Cchip CSRs, 0x801.A000.0000, 256MB. */
|
||||
memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB);
|
||||
memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",
|
||||
256*MB);
|
||||
memory_region_add_subregion(addr_space, 0x801a0000000ULL,
|
||||
&s->cchip.region);
|
||||
|
||||
/* Dchip CSRs, 0x801.B000.0000, 256MB. */
|
||||
memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB);
|
||||
memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",
|
||||
256*MB);
|
||||
memory_region_add_subregion(addr_space, 0x801b0000000ULL,
|
||||
&s->dchip_region);
|
||||
|
||||
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
|
||||
memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB);
|
||||
memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB);
|
||||
memory_region_add_subregion(addr_space, 0x80000000000ULL,
|
||||
&s->pchip.reg_mem);
|
||||
|
||||
|
|
@ -773,8 +776,8 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
|
|||
/* ??? Ideally we drop the "system" i/o space on the floor and give the
|
||||
PCI subsystem the full address space reserved by the chipset.
|
||||
We can't do that until the MEM and IO paths in memory.c are unified. */
|
||||
memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL,
|
||||
"pci0-io", 32*MB);
|
||||
memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_bw_io_ops,
|
||||
NULL, "pci0-io", 32*MB);
|
||||
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
|
||||
&s->pchip.reg_io);
|
||||
|
||||
|
|
@ -784,13 +787,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
|
|||
phb->bus = b;
|
||||
|
||||
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
|
||||
memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
|
||||
memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, b,
|
||||
"pci0-iack", 64*MB);
|
||||
memory_region_add_subregion(addr_space, 0x801f8000000ULL,
|
||||
&s->pchip.reg_iack);
|
||||
|
||||
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
|
||||
memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b,
|
||||
memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, b,
|
||||
"pci0-conf", 16*MB);
|
||||
memory_region_add_subregion(addr_space, 0x801fe000000ULL,
|
||||
&s->pchip.reg_conf);
|
||||
|
|
|
|||
|
|
@ -124,8 +124,8 @@ static int bitband_init(SysBusDevice *dev)
|
|||
{
|
||||
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
|
||||
0x02000000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &bitband_ops, &s->base,
|
||||
"bitband", 0x02000000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -203,11 +203,11 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
|
|||
#endif
|
||||
|
||||
/* Flash programming is done via the SCU, so pretend it is ROM. */
|
||||
memory_region_init_ram(flash, "armv7m.flash", flash_size);
|
||||
memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
|
||||
vmstate_register_ram_global(flash);
|
||||
memory_region_set_readonly(flash, true);
|
||||
memory_region_add_subregion(address_space_mem, 0, flash);
|
||||
memory_region_init_ram(sram, "armv7m.sram", sram_size);
|
||||
memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
|
||||
vmstate_register_ram_global(sram);
|
||||
memory_region_add_subregion(address_space_mem, 0x20000000, sram);
|
||||
armv7m_bitband_init();
|
||||
|
|
@ -247,7 +247,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
|
|||
/* Hack to map an additional page of ram at the top of the address
|
||||
space. This stops qemu complaining about executing code outside RAM
|
||||
when returning from an exception. */
|
||||
memory_region_init_ram(hack, "armv7m.hack", 0x1000);
|
||||
memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
|
||||
vmstate_register_ram_global(hack);
|
||||
memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
|
||||
|
||||
|
|
|
|||
|
|
@ -241,20 +241,20 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
|
|||
/*** Memory ***/
|
||||
|
||||
/* Chip-ID and OMR */
|
||||
memory_region_init_io(&s->chipid_mem, &exynos4210_chipid_and_omr_ops,
|
||||
memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
|
||||
NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
|
||||
memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
|
||||
&s->chipid_mem);
|
||||
|
||||
/* Internal ROM */
|
||||
memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
|
||||
memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
|
||||
EXYNOS4210_IROM_SIZE);
|
||||
vmstate_register_ram_global(&s->irom_mem);
|
||||
memory_region_set_readonly(&s->irom_mem, true);
|
||||
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
|
||||
&s->irom_mem);
|
||||
/* mirror of iROM */
|
||||
memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
|
||||
memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
|
||||
&s->irom_mem,
|
||||
0,
|
||||
EXYNOS4210_IROM_SIZE);
|
||||
|
|
@ -263,7 +263,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
|
|||
&s->irom_alias_mem);
|
||||
|
||||
/* Internal RAM */
|
||||
memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
|
||||
memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
|
||||
EXYNOS4210_IRAM_SIZE);
|
||||
vmstate_register_ram_global(&s->iram_mem);
|
||||
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
|
||||
|
|
@ -272,14 +272,14 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
|
|||
/* DRAM */
|
||||
mem_size = ram_size;
|
||||
if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
|
||||
memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
|
||||
memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
|
||||
mem_size - EXYNOS4210_DRAM_MAX_SIZE);
|
||||
vmstate_register_ram_global(&s->dram1_mem);
|
||||
memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
|
||||
&s->dram1_mem);
|
||||
mem_size = EXYNOS4210_DRAM_MAX_SIZE;
|
||||
}
|
||||
memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
|
||||
memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size);
|
||||
vmstate_register_ram_global(&s->dram0_mem);
|
||||
memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
|
||||
&s->dram0_mem);
|
||||
|
|
|
|||
|
|
@ -149,8 +149,8 @@ static int highbank_regs_init(SysBusDevice *dev)
|
|||
HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
|
||||
|
||||
s->iomem = g_new(MemoryRegion, 1);
|
||||
memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
|
||||
0x1000);
|
||||
memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
|
||||
"highbank_regs", 0x1000);
|
||||
sysbus_init_mmio(dev, s->iomem);
|
||||
|
||||
return 0;
|
||||
|
|
@ -227,12 +227,12 @@ static void highbank_init(QEMUMachineInitArgs *args)
|
|||
|
||||
sysmem = get_system_memory();
|
||||
dram = g_new(MemoryRegion, 1);
|
||||
memory_region_init_ram(dram, "highbank.dram", ram_size);
|
||||
memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
|
||||
/* SDRAM at address zero. */
|
||||
memory_region_add_subregion(sysmem, 0, dram);
|
||||
|
||||
sysram = g_new(MemoryRegion, 1);
|
||||
memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
|
||||
memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
|
||||
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
|
||||
if (bios_name != NULL) {
|
||||
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
||||
|
|
|
|||
|
|
@ -249,10 +249,10 @@ static int integratorcm_init(SysBusDevice *dev)
|
|||
}
|
||||
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
|
||||
s->cm_init = 0x00000112;
|
||||
memory_region_init_ram(&s->flash, "integrator.flash", 0x100000);
|
||||
memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000);
|
||||
vmstate_register_ram_global(&s->flash);
|
||||
|
||||
memory_region_init_io(&s->iomem, &integratorcm_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s,
|
||||
"integratorcm", 0x00800000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
@ -374,7 +374,8 @@ static int icp_pic_init(SysBusDevice *dev)
|
|||
qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
|
||||
sysbus_init_irq(dev, &s->parent_irq);
|
||||
sysbus_init_irq(dev, &s->parent_fiq);
|
||||
memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s,
|
||||
"icp-pic", 0x00800000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -424,7 +425,7 @@ static void icp_control_init(hwaddr base)
|
|||
MemoryRegion *io;
|
||||
|
||||
io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
|
||||
memory_region_init_io(io, &icp_control_ops, NULL,
|
||||
memory_region_init_io(io, NULL, &icp_control_ops, NULL,
|
||||
"control", 0x00800000);
|
||||
memory_region_add_subregion(get_system_memory(), base, io);
|
||||
/* ??? Save/restore. */
|
||||
|
|
@ -463,14 +464,14 @@ static void integratorcp_init(QEMUMachineInitArgs *args)
|
|||
exit(1);
|
||||
}
|
||||
|
||||
memory_region_init_ram(ram, "integrator.ram", ram_size);
|
||||
memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
|
||||
vmstate_register_ram_global(ram);
|
||||
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
|
||||
/* ??? RAM should repeat to fill physical memory space. */
|
||||
/* SDRAM at address zero*/
|
||||
memory_region_add_subregion(address_space_mem, 0, ram);
|
||||
/* And again at address 0x80000000 */
|
||||
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
|
||||
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
|
||||
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
|
||||
|
||||
dev = qdev_create(NULL, "integrator_core");
|
||||
|
|
|
|||
|
|
@ -98,14 +98,14 @@ static void kzm_init(QEMUMachineInitArgs *args)
|
|||
|
||||
/* On a real system, the first 16k is a `secure boot rom' */
|
||||
|
||||
memory_region_init_ram(ram, "kzm.ram", ram_size);
|
||||
memory_region_init_ram(ram, NULL, "kzm.ram", ram_size);
|
||||
vmstate_register_ram_global(ram);
|
||||
memory_region_add_subregion(address_space_mem, KZM_RAMADDRESS, ram);
|
||||
|
||||
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
|
||||
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
|
||||
memory_region_add_subregion(address_space_mem, 0x88000000, ram_alias);
|
||||
|
||||
memory_region_init_ram(sram, "kzm.sram", 0x4000);
|
||||
memory_region_init_ram(sram, NULL, "kzm.sram", 0x4000);
|
||||
memory_region_add_subregion(address_space_mem, 0x1FFFC000, sram);
|
||||
|
||||
cpu_pic = arm_pic_init_cpu(cpu);
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
|
|||
|
||||
/* Setup CPU & memory */
|
||||
mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
|
||||
memory_region_init_ram(rom, "mainstone.rom", MAINSTONE_ROM);
|
||||
memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
|
||||
vmstate_register_ram_global(rom);
|
||||
memory_region_set_readonly(rom, true);
|
||||
memory_region_add_subregion(address_space_mem, 0, rom);
|
||||
|
|
|
|||
|
|
@ -389,8 +389,8 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->irq);
|
||||
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
|
||||
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
|
||||
memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
|
||||
MP_ETH_SIZE);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_eth_ops, s,
|
||||
"mv88w8618-eth", MP_ETH_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -612,7 +612,7 @@ static int musicpal_lcd_init(SysBusDevice *dev)
|
|||
|
||||
s->brightness = 7;
|
||||
|
||||
memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_lcd_ops, s,
|
||||
"musicpal-lcd", MP_LCD_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
@ -740,7 +740,7 @@ static int mv88w8618_pic_init(SysBusDevice *dev)
|
|||
|
||||
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
|
||||
sysbus_init_irq(dev, &s->parent_irq);
|
||||
memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pic_ops, s,
|
||||
"musicpal-pic", MP_PIC_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
|
|
@ -905,7 +905,7 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
|
|||
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pit_ops, s,
|
||||
"musicpal-pit", MP_PIT_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
|
|
@ -999,7 +999,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
|
|||
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
|
||||
|
||||
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
|
||||
memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_flashcfg_ops, s,
|
||||
"musicpal-flashcfg", MP_FLASHCFG_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
|
|
@ -1074,7 +1074,7 @@ static void musicpal_misc_init(Object *obj)
|
|||
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
|
||||
MusicPalMiscState *s = MUSICPAL_MISC(obj);
|
||||
|
||||
memory_region_init_io(&s->iomem, &musicpal_misc_ops, NULL,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL,
|
||||
"musicpal-misc", MP_MISC_SIZE);
|
||||
sysbus_init_mmio(sd, &s->iomem);
|
||||
}
|
||||
|
|
@ -1121,7 +1121,7 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
|
|||
{
|
||||
MemoryRegion *iomem = g_new(MemoryRegion, 1);
|
||||
|
||||
memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
|
||||
memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL,
|
||||
"musicpal-wlan", MP_WLAN_SIZE);
|
||||
sysbus_init_mmio(dev, iomem);
|
||||
return 0;
|
||||
|
|
@ -1327,7 +1327,7 @@ static int musicpal_gpio_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_gpio_ops, s,
|
||||
"musicpal-gpio", MP_GPIO_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
@ -1484,7 +1484,7 @@ static int musicpal_key_init(SysBusDevice *dev)
|
|||
{
|
||||
musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
|
||||
|
||||
memory_region_init(&s->iomem, "dummy", 0);
|
||||
memory_region_init(&s->iomem, OBJECT(s), "dummy", 0);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
s->kbd_extended = 0;
|
||||
|
|
@ -1564,11 +1564,11 @@ static void musicpal_init(QEMUMachineInitArgs *args)
|
|||
cpu_pic = arm_pic_init_cpu(cpu);
|
||||
|
||||
/* For now we use a fixed - the original - RAM size */
|
||||
memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
|
||||
memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
|
||||
vmstate_register_ram_global(ram);
|
||||
memory_region_add_subregion(address_space_mem, 0, ram);
|
||||
|
||||
memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
|
||||
memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
|
||||
vmstate_register_ram_global(sram);
|
||||
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
|
||||
|
||||
|
|
|
|||
|
|
@ -264,7 +264,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
|
|||
omap_mpu_timer_reset(s);
|
||||
omap_timer_clk_setup(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
|
||||
"omap-mpu-timer", 0x100);
|
||||
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
|
|
@ -392,7 +392,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
|
|||
omap_wd_timer_reset(s);
|
||||
omap_timer_clk_setup(&s->timer);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
|
||||
"omap-wd-timer", 0x100);
|
||||
memory_region_add_subregion(memory, base, &s->iomem);
|
||||
|
||||
|
|
@ -498,7 +498,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
|
|||
omap_os_timer_reset(s);
|
||||
omap_timer_clk_setup(&s->timer);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
|
||||
"omap-os-timer", 0x800);
|
||||
memory_region_add_subregion(memory, base, &s->iomem);
|
||||
|
||||
|
|
@ -731,7 +731,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
|
|||
hwaddr base,
|
||||
struct omap_mpu_state_s *mpu)
|
||||
{
|
||||
memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
|
||||
memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
|
||||
"omap-ulpd-pm", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
|
||||
omap_ulpd_pm_reset(mpu);
|
||||
|
|
@ -949,7 +949,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
|
|||
hwaddr base,
|
||||
struct omap_mpu_state_s *mpu)
|
||||
{
|
||||
memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
|
||||
memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
|
||||
"omap-pin-cfg", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
|
||||
omap_pin_cfg_reset(mpu);
|
||||
|
|
@ -1021,16 +1021,16 @@ static const MemoryRegionOps omap_id_ops = {
|
|||
|
||||
static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
|
||||
{
|
||||
memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
|
||||
memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
|
||||
"omap-id", 0x100000000ULL);
|
||||
memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
|
||||
memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
|
||||
0xfffe1800, 0x800);
|
||||
memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
|
||||
memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
|
||||
memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
|
||||
0xfffed400, 0x100);
|
||||
memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
|
||||
if (!cpu_is_omap15xx(mpu)) {
|
||||
memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
|
||||
memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
|
||||
&mpu->id_iomem, 0xfffe2000, 0x800);
|
||||
memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
|
||||
}
|
||||
|
|
@ -1115,7 +1115,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
|
|||
static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
|
||||
struct omap_mpu_state_s *mpu)
|
||||
{
|
||||
memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
|
||||
memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
|
||||
"omap-mpui", 0x100);
|
||||
memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
|
||||
|
||||
|
|
@ -1227,7 +1227,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
|
|||
s->abort = abort_irq;
|
||||
omap_tipb_bridge_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
|
||||
"omap-tipb-bridge", 0x100);
|
||||
memory_region_add_subregion(memory, base, &s->iomem);
|
||||
|
||||
|
|
@ -1336,7 +1336,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
|
|||
static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
|
||||
struct omap_mpu_state_s *mpu)
|
||||
{
|
||||
memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
|
||||
memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
|
||||
"omap-tcmi", 0x100);
|
||||
memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
|
||||
omap_tcmi_reset(mpu);
|
||||
|
|
@ -1418,7 +1418,7 @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
|
|||
hwaddr base, omap_clk clk)
|
||||
{
|
||||
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
|
||||
memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
|
||||
|
||||
s->dpll = clk;
|
||||
omap_dpll_reset(s);
|
||||
|
|
@ -1831,9 +1831,9 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
|
|||
static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
|
||||
hwaddr dsp_base, struct omap_mpu_state_s *s)
|
||||
{
|
||||
memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
|
||||
memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
|
||||
"omap-clkm", 0x100);
|
||||
memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
|
||||
memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
|
||||
"omap-clkdsp", 0x1000);
|
||||
|
||||
s->clkm.arm_idlect1 = 0x03ff;
|
||||
|
|
@ -2090,7 +2090,7 @@ static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
|
|||
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
||||
omap_mpuio_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
|
||||
"omap-mpuio", 0x800);
|
||||
memory_region_add_subregion(memory, base, &s->iomem);
|
||||
|
||||
|
|
@ -2281,7 +2281,7 @@ static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
|
|||
s->txdrq = dma;
|
||||
omap_uwire_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
|
||||
return s;
|
||||
|
|
@ -2393,7 +2393,7 @@ static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
|
|||
|
||||
omap_pwl_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_pwl_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
|
||||
"omap-pwl", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
|
||||
|
|
@ -2500,7 +2500,7 @@ static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
|
|||
s->clk = clk;
|
||||
omap_pwt_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_pwt_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
|
||||
"omap-pwt", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
return s;
|
||||
|
|
@ -2919,7 +2919,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
|
|||
|
||||
omap_rtc_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
|
||||
"omap-rtc", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
|
||||
|
|
@ -3452,7 +3452,7 @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
|
|||
s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
|
||||
omap_mcbsp_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
|
||||
return s;
|
||||
|
|
@ -3627,7 +3627,7 @@ static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
|
|||
|
||||
omap_lpg_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
|
||||
memory_region_add_subregion(system_memory, base, &s->iomem);
|
||||
|
||||
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
|
||||
|
|
@ -3666,7 +3666,7 @@ static const MemoryRegionOps omap_mpui_io_ops = {
|
|||
static void omap_setup_mpui_io(MemoryRegion *system_memory,
|
||||
struct omap_mpu_state_s *mpu)
|
||||
{
|
||||
memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
|
||||
memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
|
||||
"omap-mpui-io", 0x7fff);
|
||||
memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
|
||||
&mpu->mpui_io_iomem);
|
||||
|
|
@ -3747,7 +3747,7 @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
|
|||
|
||||
for (; map->phys_dsp; map ++) {
|
||||
io = g_new(MemoryRegion, 1);
|
||||
memory_region_init_alias(io, map->name,
|
||||
memory_region_init_alias(io, NULL, map->name,
|
||||
system_memory, map->phys_mpu, map->size);
|
||||
memory_region_add_subregion(system_memory, map->phys_dsp, io);
|
||||
}
|
||||
|
|
@ -3851,10 +3851,10 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
|
|||
omap_clk_init(s);
|
||||
|
||||
/* Memory-mapped stuff */
|
||||
memory_region_init_ram(&s->emiff_ram, "omap1.dram", s->sdram_size);
|
||||
memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
|
||||
vmstate_register_ram_global(&s->emiff_ram);
|
||||
memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
|
||||
memory_region_init_ram(&s->imif_ram, "omap1.sram", s->sram_size);
|
||||
memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
|
||||
vmstate_register_ram_global(&s->imif_ram);
|
||||
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
|
||||
|
||||
|
|
|
|||
|
|
@ -603,7 +603,7 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
|
|||
|
||||
AUD_register_card("OMAP EAC", &s->codec.card);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_eac_ops, s, "omap.eac",
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
|
||||
omap_l4_region_size(ta, 0));
|
||||
omap_l4_attach(ta, 0, &s->iomem);
|
||||
|
||||
|
|
@ -791,11 +791,11 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
|
|||
|
||||
s->chr = chr ?: qemu_chr_new("null", "null", NULL);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_sti_ops, s, "omap.sti",
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
|
||||
omap_l4_region_size(ta, 0));
|
||||
omap_l4_attach(ta, 0, &s->iomem);
|
||||
|
||||
memory_region_init_io(&s->iomem_fifo, &omap_sti_fifo_ops, s,
|
||||
memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
|
||||
"omap.sti.fifo", 0x10000);
|
||||
memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
|
||||
|
||||
|
|
@ -1809,9 +1809,9 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
|
|||
s->mpu = mpu;
|
||||
omap_prcm_coldreset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem0, &omap_prcm_ops, s, "omap.pcrm0",
|
||||
memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
|
||||
omap_l4_region_size(ta, 0));
|
||||
memory_region_init_io(&s->iomem1, &omap_prcm_ops, s, "omap.pcrm1",
|
||||
memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
|
||||
omap_l4_region_size(ta, 1));
|
||||
omap_l4_attach(ta, 0, &s->iomem0);
|
||||
omap_l4_attach(ta, 1, &s->iomem1);
|
||||
|
|
@ -2185,7 +2185,7 @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
|
|||
s->mpu = mpu;
|
||||
omap_sysctl_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_sysctl_ops, s, "omap.sysctl",
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
|
||||
omap_l4_region_size(ta, 0));
|
||||
omap_l4_attach(ta, 0, &s->iomem);
|
||||
|
||||
|
|
@ -2267,10 +2267,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
|
|||
omap_clk_init(s);
|
||||
|
||||
/* Memory-mapped stuff */
|
||||
memory_region_init_ram(&s->sdram, "omap2.dram", s->sdram_size);
|
||||
memory_region_init_ram(&s->sdram, NULL, "omap2.dram", s->sdram_size);
|
||||
vmstate_register_ram_global(&s->sdram);
|
||||
memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
|
||||
memory_region_init_ram(&s->sram, "omap2.sram", s->sram_size);
|
||||
memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size);
|
||||
vmstate_register_ram_global(&s->sram);
|
||||
memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
|
||||
|
||||
|
|
|
|||
|
|
@ -120,23 +120,23 @@ static void sx1_init(QEMUMachineInitArgs *args, const int version)
|
|||
mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, args->cpu_model);
|
||||
|
||||
/* External Flash (EMIFS) */
|
||||
memory_region_init_ram(flash, "omap_sx1.flash0-0", flash_size);
|
||||
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size);
|
||||
vmstate_register_ram_global(flash);
|
||||
memory_region_set_readonly(flash, true);
|
||||
memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
|
||||
|
||||
memory_region_init_io(&cs[0], &static_ops, &cs0val,
|
||||
memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,
|
||||
"sx1.cs0", OMAP_CS0_SIZE - flash_size);
|
||||
memory_region_add_subregion(address_space,
|
||||
OMAP_CS0_BASE + flash_size, &cs[0]);
|
||||
|
||||
|
||||
memory_region_init_io(&cs[2], &static_ops, &cs2val,
|
||||
memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val,
|
||||
"sx1.cs2", OMAP_CS2_SIZE);
|
||||
memory_region_add_subregion(address_space,
|
||||
OMAP_CS2_BASE, &cs[2]);
|
||||
|
||||
memory_region_init_io(&cs[3], &static_ops, &cs3val,
|
||||
memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val,
|
||||
"sx1.cs3", OMAP_CS3_SIZE);
|
||||
memory_region_add_subregion(address_space,
|
||||
OMAP_CS2_BASE, &cs[3]);
|
||||
|
|
@ -162,12 +162,12 @@ static void sx1_init(QEMUMachineInitArgs *args, const int version)
|
|||
|
||||
if ((version == 1) &&
|
||||
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
|
||||
memory_region_init_ram(flash_1, "omap_sx1.flash1-0", flash1_size);
|
||||
memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size);
|
||||
vmstate_register_ram_global(flash_1);
|
||||
memory_region_set_readonly(flash_1, true);
|
||||
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
|
||||
|
||||
memory_region_init_io(&cs[1], &static_ops, &cs1val,
|
||||
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
|
||||
"sx1.cs1", OMAP_CS1_SIZE - flash1_size);
|
||||
memory_region_add_subregion(address_space,
|
||||
OMAP_CS1_BASE + flash1_size, &cs[1]);
|
||||
|
|
@ -182,7 +182,7 @@ static void sx1_init(QEMUMachineInitArgs *args, const int version)
|
|||
}
|
||||
fl_idx++;
|
||||
} else {
|
||||
memory_region_init_io(&cs[1], &static_ops, &cs1val,
|
||||
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
|
||||
"sx1.cs1", OMAP_CS1_SIZE);
|
||||
memory_region_add_subregion(address_space,
|
||||
OMAP_CS1_BASE, &cs[1]);
|
||||
|
|
|
|||
|
|
@ -211,22 +211,22 @@ static void palmte_init(QEMUMachineInitArgs *args)
|
|||
mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
|
||||
|
||||
/* External Flash (EMIFS) */
|
||||
memory_region_init_ram(flash, "palmte.flash", flash_size);
|
||||
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size);
|
||||
vmstate_register_ram_global(flash);
|
||||
memory_region_set_readonly(flash, true);
|
||||
memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE, flash);
|
||||
|
||||
memory_region_init_io(&cs[0], &static_ops, &cs0val, "palmte-cs0",
|
||||
memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val, "palmte-cs0",
|
||||
OMAP_CS0_SIZE - flash_size);
|
||||
memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE + flash_size,
|
||||
&cs[0]);
|
||||
memory_region_init_io(&cs[1], &static_ops, &cs1val, "palmte-cs1",
|
||||
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, "palmte-cs1",
|
||||
OMAP_CS1_SIZE);
|
||||
memory_region_add_subregion(address_space_mem, OMAP_CS1_BASE, &cs[1]);
|
||||
memory_region_init_io(&cs[2], &static_ops, &cs2val, "palmte-cs2",
|
||||
memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val, "palmte-cs2",
|
||||
OMAP_CS2_SIZE);
|
||||
memory_region_add_subregion(address_space_mem, OMAP_CS2_BASE, &cs[2]);
|
||||
memory_region_init_io(&cs[3], &static_ops, &cs3val, "palmte-cs3",
|
||||
memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val, "palmte-cs3",
|
||||
OMAP_CS3_SIZE);
|
||||
memory_region_add_subregion(address_space_mem, OMAP_CS3_BASE, &cs[3]);
|
||||
|
||||
|
|
|
|||
|
|
@ -764,7 +764,8 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
|
||||
"pxa2xx-ssp", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
|
||||
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
|
||||
|
|
@ -1131,7 +1132,8 @@ static int pxa2xx_rtc_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->rtc_irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
|
||||
"pxa2xx-rtc", 0x10000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1481,8 +1483,8 @@ static int pxa2xx_i2c_initfn(SysBusDevice *dev)
|
|||
|
||||
s->bus = i2c_init_bus(&dev->qdev, "i2c");
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s,
|
||||
"pxa2xx-i2x", s->region_size);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
|
||||
"pxa2xx-i2c", s->region_size);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
|
|
@ -1720,7 +1722,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
|
|||
|
||||
pxa2xx_i2s_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
|
||||
"pxa2xx-i2s", 0x100000);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
|
|
@ -1978,7 +1980,7 @@ static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
|
|||
|
||||
pxa2xx_fir_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
|
||||
memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
if (chr) {
|
||||
|
|
@ -2027,10 +2029,10 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
|
|||
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
|
||||
|
||||
/* SDRAM & Internal Memory Storage */
|
||||
memory_region_init_ram(&s->sdram, "pxa270.sdram", sdram_size);
|
||||
memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
|
||||
vmstate_register_ram_global(&s->sdram);
|
||||
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
|
||||
memory_region_init_ram(&s->internal, "pxa270.internal", 0x40000);
|
||||
memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
|
||||
vmstate_register_ram_global(&s->internal);
|
||||
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
|
||||
&s->internal);
|
||||
|
|
@ -2083,7 +2085,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
|
|||
s->cm_base = 0x41300000;
|
||||
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
|
||||
s->clkcfg = 0x00000009; /* Turbo mode active */
|
||||
memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
|
||||
memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
|
||||
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
|
||||
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
|
||||
|
||||
|
|
@ -2093,12 +2095,12 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
|
|||
s->mm_regs[MDMRS >> 2] = 0x00020002;
|
||||
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
|
||||
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
|
||||
memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
|
||||
memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
|
||||
memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
|
||||
vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
|
||||
|
||||
s->pm_base = 0x40f00000;
|
||||
memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
|
||||
memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
|
||||
memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
|
||||
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
|
||||
|
||||
|
|
@ -2158,10 +2160,10 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
|
|||
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
|
||||
|
||||
/* SDRAM & Internal Memory Storage */
|
||||
memory_region_init_ram(&s->sdram, "pxa255.sdram", sdram_size);
|
||||
memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
|
||||
vmstate_register_ram_global(&s->sdram);
|
||||
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
|
||||
memory_region_init_ram(&s->internal, "pxa255.internal",
|
||||
memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
|
||||
PXA2XX_INTERNAL_SIZE);
|
||||
vmstate_register_ram_global(&s->internal);
|
||||
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
|
||||
|
|
@ -2214,7 +2216,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
|
|||
s->cm_base = 0x41300000;
|
||||
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
|
||||
s->clkcfg = 0x00000009; /* Turbo mode active */
|
||||
memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
|
||||
memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
|
||||
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
|
||||
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
|
||||
|
||||
|
|
@ -2224,12 +2226,12 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
|
|||
s->mm_regs[MDMRS >> 2] = 0x00020002;
|
||||
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
|
||||
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
|
||||
memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
|
||||
memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
|
||||
memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
|
||||
vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
|
||||
|
||||
s->pm_base = 0x40f00000;
|
||||
memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
|
||||
memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
|
||||
memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
|
||||
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
|
||||
|
||||
|
|
|
|||
|
|
@ -283,7 +283,7 @@ static int pxa2xx_gpio_initfn(SysBusDevice *dev)
|
|||
qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
|
||||
qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq0);
|
||||
sysbus_init_irq(dev, &s->irq1);
|
||||
|
|
|
|||
|
|
@ -278,7 +278,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
|
|||
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
|
||||
|
||||
/* Enable IC memory-mapped registers access. */
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
|
||||
"pxa2xx-pic", 0x00100000);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
||||
|
|
|
|||
|
|
@ -114,18 +114,18 @@ static void realview_init(QEMUMachineInitArgs *args,
|
|||
/* Core tile RAM. */
|
||||
low_ram_size = ram_size - 0x20000000;
|
||||
ram_size = 0x20000000;
|
||||
memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size);
|
||||
memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size);
|
||||
vmstate_register_ram_global(ram_lo);
|
||||
memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
|
||||
}
|
||||
|
||||
memory_region_init_ram(ram_hi, "realview.highmem", ram_size);
|
||||
memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size);
|
||||
vmstate_register_ram_global(ram_hi);
|
||||
low_ram_size = ram_size;
|
||||
if (low_ram_size > 0x10000000)
|
||||
low_ram_size = 0x10000000;
|
||||
/* SDRAM at address zero. */
|
||||
memory_region_init_alias(ram_alias, "realview.alias",
|
||||
memory_region_init_alias(ram_alias, NULL, "realview.alias",
|
||||
ram_hi, 0, low_ram_size);
|
||||
memory_region_add_subregion(sysmem, 0, ram_alias);
|
||||
if (is_pb) {
|
||||
|
|
@ -318,7 +318,7 @@ static void realview_init(QEMUMachineInitArgs *args,
|
|||
startup code. I guess this works on real hardware because the
|
||||
BootROM happens to be in ROM/flash or in memory that isn't clobbered
|
||||
until after Linux boots the secondary CPUs. */
|
||||
memory_region_init_ram(ram_hack, "realview.hack", 0x1000);
|
||||
memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000);
|
||||
vmstate_register_ram_global(ram_hack);
|
||||
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
|
||||
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@ static int sl_nand_init(SysBusDevice *dev) {
|
|||
nand = drive_get(IF_MTD, 0, 0);
|
||||
s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
|
||||
|
||||
memory_region_init_io(&s->iomem, &sl_ops, s, "sl", 0x40);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &sl_ops, s, "sl", 0x40);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
return 0;
|
||||
|
|
@ -896,7 +896,7 @@ static void spitz_common_init(QEMUMachineInitArgs *args,
|
|||
|
||||
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
|
||||
|
||||
memory_region_init_ram(rom, "spitz.rom", SPITZ_ROM);
|
||||
memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM);
|
||||
vmstate_register_ram_global(rom);
|
||||
memory_region_set_readonly(rom, true);
|
||||
memory_region_add_subregion(address_space_mem, 0, rom);
|
||||
|
|
|
|||
|
|
@ -307,7 +307,7 @@ static int stellaris_gptm_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->irq);
|
||||
qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
|
||||
|
||||
memory_region_init_io(&s->iomem, &gptm_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s,
|
||||
"gptm", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
@ -669,7 +669,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
|
|||
s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
|
||||
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
|
||||
|
||||
memory_region_init_io(&s->iomem, &ssys_ops, s, "ssys", 0x00001000);
|
||||
memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
|
||||
memory_region_add_subregion(get_system_memory(), base, &s->iomem);
|
||||
ssys_reset(s);
|
||||
vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
|
||||
|
|
@ -862,7 +862,7 @@ static int stellaris_i2c_init(SysBusDevice * dev)
|
|||
bus = i2c_init_bus(&dev->qdev, "i2c");
|
||||
s->bus = bus;
|
||||
|
||||
memory_region_init_io(&s->iomem, &stellaris_i2c_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s,
|
||||
"i2c", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
/* ??? For now we only implement the master interface. */
|
||||
|
|
@ -1145,7 +1145,7 @@ static int stellaris_adc_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->irq[n]);
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->iomem, &stellaris_adc_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s,
|
||||
"adc", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
stellaris_adc_reset(s);
|
||||
|
|
|
|||
|
|
@ -173,7 +173,8 @@ static int strongarm_pic_initfn(SysBusDevice *dev)
|
|||
StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
|
||||
|
||||
qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
|
||||
memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
|
||||
"pic", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
sysbus_init_irq(dev, &s->fiq);
|
||||
|
|
@ -383,7 +384,8 @@ static int strongarm_rtc_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->rtc_irq);
|
||||
sysbus_init_irq(dev, &s->rtc_hz_irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
|
||||
"rtc", 0x10000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
return 0;
|
||||
|
|
@ -637,7 +639,8 @@ static int strongarm_gpio_initfn(SysBusDevice *dev)
|
|||
qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
|
||||
qdev_init_gpio_out(&dev->qdev, s->handler, 28);
|
||||
|
||||
memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
|
||||
"gpio", 0x1000);
|
||||
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
for (i = 0; i < 11; i++) {
|
||||
|
|
@ -808,7 +811,8 @@ static int strongarm_ppc_init(SysBusDevice *dev)
|
|||
qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
|
||||
qdev_init_gpio_out(&dev->qdev, s->handler, 22);
|
||||
|
||||
memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
|
||||
"ppc", 0x1000);
|
||||
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
@ -1204,7 +1208,8 @@ static int strongarm_uart_init(SysBusDevice *dev)
|
|||
{
|
||||
StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
|
||||
"uart", 0x10000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
|
|
@ -1496,7 +1501,8 @@ static int strongarm_ssp_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s,
|
||||
"ssp", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
s->bus = ssi_create_bus(&dev->qdev, "ssi");
|
||||
|
|
@ -1571,7 +1577,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
|
|||
exit(1);
|
||||
}
|
||||
|
||||
memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
|
||||
memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size);
|
||||
vmstate_register_ram_global(&s->sdram);
|
||||
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
|
||||
|
||||
|
|
|
|||
|
|
@ -222,7 +222,7 @@ static void tosa_init(QEMUMachineInitArgs *args)
|
|||
|
||||
mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
|
||||
|
||||
memory_region_init_ram(rom, "tosa.rom", TOSA_ROM);
|
||||
memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM);
|
||||
vmstate_register_ram_global(rom);
|
||||
memory_region_set_readonly(rom, true);
|
||||
memory_region_add_subregion(address_space_mem, 0, rom);
|
||||
|
|
|
|||
|
|
@ -154,7 +154,8 @@ static int vpb_sic_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->parent[i]);
|
||||
}
|
||||
s->irq = 31;
|
||||
memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
|
||||
"vpb-sic", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -193,7 +194,7 @@ static void versatile_init(QEMUMachineInitArgs *args, int board_id)
|
|||
fprintf(stderr, "Unable to find CPU definition\n");
|
||||
exit(1);
|
||||
}
|
||||
memory_region_init_ram(ram, "versatile.ram", args->ram_size);
|
||||
memory_region_init_ram(ram, NULL, "versatile.ram", args->ram_size);
|
||||
vmstate_register_ram_global(ram);
|
||||
/* ??? RAM should repeat to fill physical memory space. */
|
||||
/* SDRAM at address zero. */
|
||||
|
|
|
|||
|
|
@ -196,7 +196,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
|
|||
exit(1);
|
||||
}
|
||||
|
||||
memory_region_init_ram(ram, "vexpress.highmem", ram_size);
|
||||
memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
|
||||
vmstate_register_ram_global(ram);
|
||||
low_ram_size = ram_size;
|
||||
if (low_ram_size > 0x4000000) {
|
||||
|
|
@ -206,7 +206,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
|
|||
* address space should in theory be remappable to various
|
||||
* things including ROM or RAM; we always map the RAM there.
|
||||
*/
|
||||
memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
|
||||
memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
|
||||
memory_region_add_subregion(sysmem, 0x0, lowram);
|
||||
memory_region_add_subregion(sysmem, 0x60000000, ram);
|
||||
|
||||
|
|
@ -323,7 +323,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
|
|||
}
|
||||
}
|
||||
|
||||
memory_region_init_ram(ram, "vexpress.highmem", ram_size);
|
||||
memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
|
||||
vmstate_register_ram_global(ram);
|
||||
/* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
|
||||
memory_region_add_subregion(sysmem, 0x80000000, ram);
|
||||
|
|
@ -357,7 +357,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
|
|||
/* 0x2b060000: SP805 watchdog: not modelled */
|
||||
/* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
|
||||
/* 0x2e000000: system SRAM */
|
||||
memory_region_init_ram(sram, "vexpress.a15sram", 0x10000);
|
||||
memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000);
|
||||
vmstate_register_ram_global(sram);
|
||||
memory_region_add_subregion(sysmem, 0x2e000000, sram);
|
||||
|
||||
|
|
@ -491,12 +491,12 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
|
|||
}
|
||||
|
||||
sram_size = 0x2000000;
|
||||
memory_region_init_ram(sram, "vexpress.sram", sram_size);
|
||||
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size);
|
||||
vmstate_register_ram_global(sram);
|
||||
memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
|
||||
|
||||
vram_size = 0x800000;
|
||||
memory_region_init_ram(vram, "vexpress.vram", vram_size);
|
||||
memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size);
|
||||
vmstate_register_ram_global(vram);
|
||||
memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
|
||||
|
||||
|
|
|
|||
|
|
@ -132,12 +132,12 @@ static void zynq_init(QEMUMachineInitArgs *args)
|
|||
}
|
||||
|
||||
/* DDR remapped to address zero. */
|
||||
memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
|
||||
memory_region_init_ram(ext_ram, NULL, "zynq.ext_ram", ram_size);
|
||||
vmstate_register_ram_global(ext_ram);
|
||||
memory_region_add_subregion(address_space_mem, 0, ext_ram);
|
||||
|
||||
/* 256K of on-chip memory */
|
||||
memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
|
||||
memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10);
|
||||
vmstate_register_ram_global(ocm_ram);
|
||||
memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
|
||||
|
||||
|
|
|
|||
|
|
@ -1378,8 +1378,10 @@ static int ac97_initfn (PCIDevice *dev)
|
|||
c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
|
||||
c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
|
||||
|
||||
memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
|
||||
memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
|
||||
memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s,
|
||||
"ac97-nam", 1024);
|
||||
memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s,
|
||||
"ac97-nabm", 256);
|
||||
pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
|
||||
pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
|
||||
qemu_register_reset (ac97_on_reset, s);
|
||||
|
|
|
|||
|
|
@ -283,9 +283,17 @@ static void Adlib_fini (AdlibState *s)
|
|||
AUD_remove_card (&s->card);
|
||||
}
|
||||
|
||||
static MemoryRegionPortio adlib_portio_list[] = {
|
||||
{ 0x388, 4, 1, .read = adlib_read, .write = adlib_write, },
|
||||
{ 0, 4, 1, .read = adlib_read, .write = adlib_write, },
|
||||
{ 0, 2, 1, .read = adlib_read, .write = adlib_write, },
|
||||
PORTIO_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void adlib_realizefn (DeviceState *dev, Error **errp)
|
||||
{
|
||||
AdlibState *s = ADLIB(dev);
|
||||
PortioList *port_list = g_new(PortioList, 1);
|
||||
struct audsettings as;
|
||||
|
||||
if (glob_adlib) {
|
||||
|
|
@ -339,14 +347,10 @@ static void adlib_realizefn (DeviceState *dev, Error **errp)
|
|||
s->samples = AUD_get_buffer_size_out (s->voice) >> SHIFT;
|
||||
s->mixbuf = g_malloc0 (s->samples << SHIFT);
|
||||
|
||||
register_ioport_read (0x388, 4, 1, adlib_read, s);
|
||||
register_ioport_write (0x388, 4, 1, adlib_write, s);
|
||||
|
||||
register_ioport_read (s->port, 4, 1, adlib_read, s);
|
||||
register_ioport_write (s->port, 4, 1, adlib_write, s);
|
||||
|
||||
register_ioport_read (s->port + 8, 2, 1, adlib_read, s);
|
||||
register_ioport_write (s->port + 8, 2, 1, adlib_write, s);
|
||||
adlib_portio_list[1].offset = s->port;
|
||||
adlib_portio_list[2].offset = s->port + 8;
|
||||
portio_list_init (port_list, OBJECT(s), adlib_portio_list, s, "adlib");
|
||||
portio_list_add (port_list, isa_address_space_io(&s->parent_obj), 0);
|
||||
}
|
||||
|
||||
static Property adlib_properties[] = {
|
||||
|
|
|
|||
|
|
@ -144,7 +144,8 @@ static int cs4231_init1(SysBusDevice *dev)
|
|||
{
|
||||
CSState *s = FROM_SYSBUS(CSState, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &cs_mem_ops, s, "cs4321",
|
||||
CS_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
|
|
|
|||
|
|
@ -648,7 +648,8 @@ static void cs4231a_initfn (Object *obj)
|
|||
{
|
||||
CSState *s = CS4231A (obj);
|
||||
|
||||
memory_region_init_io (&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
|
||||
memory_region_init_io (&s->ioports, OBJECT(s), &cs_ioport_ops, s,
|
||||
"cs4231a", 4);
|
||||
}
|
||||
|
||||
static void cs4231a_realizefn (DeviceState *dev, Error **errp)
|
||||
|
|
|
|||
|
|
@ -1035,7 +1035,7 @@ static int es1370_initfn (PCIDevice *dev)
|
|||
c[PCI_MIN_GNT] = 0x0c;
|
||||
c[PCI_MAX_LAT] = 0x80;
|
||||
|
||||
memory_region_init_io (&s->io, &es1370_io_ops, s, "es1370", 256);
|
||||
memory_region_init_io (&s->io, OBJECT(s), &es1370_io_ops, s, "es1370", 256);
|
||||
pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
||||
qemu_register_reset (es1370_on_reset, s);
|
||||
|
||||
|
|
|
|||
|
|
@ -1135,7 +1135,7 @@ static int intel_hda_init(PCIDevice *pci)
|
|||
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
|
||||
conf[0x40] = 0x01;
|
||||
|
||||
memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
|
||||
memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
|
||||
"intel-hda", 0x4000);
|
||||
pci_register_bar(&d->pci, 0, 0, &d->mmio);
|
||||
if (d->msi) {
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ static int mv88w8618_audio_init(SysBusDevice *dev)
|
|||
|
||||
wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &mv88w8618_audio_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_audio_ops, s,
|
||||
"audio", MP_AUDIO_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ static int milkymist_ac97_init(SysBusDevice *dev)
|
|||
s->voice_out = AUD_open_out(&s->card, s->voice_out,
|
||||
"mm_ac97.out", s, ac97_out_cb, &as);
|
||||
|
||||
memory_region_init_io(&s->regs_region, &ac97_mmio_ops, s,
|
||||
memory_region_init_io(&s->regs_region, OBJECT(s), &ac97_mmio_ops, s,
|
||||
"milkymist-ac97", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->regs_region);
|
||||
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ static void pcspk_initfn(Object *obj)
|
|||
{
|
||||
PCSpkState *s = PC_SPEAKER(obj);
|
||||
|
||||
memory_region_init_io(&s->ioport, &pcspk_io_ops, s, "elcr", 1);
|
||||
memory_region_init_io(&s->ioport, OBJECT(s), &pcspk_io_ops, s, "elcr", 1);
|
||||
}
|
||||
|
||||
static void pcspk_realizefn(DeviceState *dev, Error **errp)
|
||||
|
|
|
|||
|
|
@ -543,7 +543,7 @@ static int pl041_init(SysBusDevice *dev)
|
|||
}
|
||||
|
||||
/* Connect the device to the sysbus */
|
||||
memory_region_init_io(&s->iomem, &pl041_ops, s, "pl041", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pl041_ops, s, "pl041", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
|
|
|
|||
|
|
@ -2149,7 +2149,8 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
|
|||
FDCtrl *fdctrl = &sys->state;
|
||||
int ret;
|
||||
|
||||
memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
|
||||
memory_region_init_io(&fdctrl->iomem, OBJECT(sys), &fdctrl_mem_ops, fdctrl,
|
||||
"fdc", 0x08);
|
||||
sysbus_init_mmio(dev, &fdctrl->iomem);
|
||||
sysbus_init_irq(dev, &fdctrl->irq);
|
||||
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
||||
|
|
@ -2165,8 +2166,8 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
|
|||
{
|
||||
FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
|
||||
|
||||
memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
|
||||
"fdctrl", 0x08);
|
||||
memory_region_init_io(&fdctrl->iomem, OBJECT(dev), &fdctrl_mem_strict_ops,
|
||||
fdctrl, "fdctrl", 0x08);
|
||||
sysbus_init_mmio(dev, &fdctrl->iomem);
|
||||
sysbus_init_irq(dev, &fdctrl->irq);
|
||||
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
||||
|
|
|
|||
|
|
@ -777,7 +777,8 @@ static int nvme_init(PCIDevice *pci_dev)
|
|||
n->sq = g_malloc0(sizeof(*n->sq)*n->num_queues);
|
||||
n->cq = g_malloc0(sizeof(*n->cq)*n->num_queues);
|
||||
|
||||
memory_region_init_io(&n->iomem, &nvme_mmio_ops, n, "nvme", n->reg_size);
|
||||
memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
|
||||
"nvme", n->reg_size);
|
||||
pci_register_bar(&n->parent_obj, 0,
|
||||
PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
|
||||
&n->iomem);
|
||||
|
|
|
|||
|
|
@ -113,9 +113,10 @@ static void onenand_mem_setup(OneNANDState *s)
|
|||
/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
|
||||
* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
|
||||
* write boot commands. Also take note of the BWPS bit. */
|
||||
memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
|
||||
memory_region_init(&s->container, OBJECT(s), "onenand",
|
||||
0x10000 << s->shift);
|
||||
memory_region_add_subregion(&s->container, 0, &s->iomem);
|
||||
memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
|
||||
memory_region_init_alias(&s->mapped_ram, OBJECT(s), "onenand-mapped-ram",
|
||||
&s->ram, 0x0200 << s->shift,
|
||||
0xbe00 << s->shift);
|
||||
memory_region_add_subregion_overlap(&s->container,
|
||||
|
|
@ -768,7 +769,7 @@ static int onenand_initfn(SysBusDevice *dev)
|
|||
s->blockwp = g_malloc(s->blocks);
|
||||
s->density_mask = (s->id.dev & 0x08)
|
||||
? (1 << (6 + ((s->id.dev >> 4) & 7))) : 0;
|
||||
memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &onenand_ops, s, "onenand",
|
||||
0x10000 << s->shift);
|
||||
if (!s->bdrv) {
|
||||
s->image = memset(g_malloc(size + (size >> 5)),
|
||||
|
|
@ -782,7 +783,8 @@ static int onenand_initfn(SysBusDevice *dev)
|
|||
}
|
||||
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
|
||||
0xff, (64 + 2) << PAGE_SHIFT);
|
||||
memory_region_init_ram(&s->ram, "onenand.ram", 0xc000 << s->shift);
|
||||
memory_region_init_ram(&s->ram, OBJECT(s), "onenand.ram",
|
||||
0xc000 << s->shift);
|
||||
vmstate_register_ram_global(&s->ram);
|
||||
ram = memory_region_get_ram_ptr(&s->ram);
|
||||
s->boot[0] = ram + (0x0000 << s->shift);
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
|
|||
isa_bios_size = 128 * 1024;
|
||||
}
|
||||
isa_bios = g_malloc(sizeof(*isa_bios));
|
||||
memory_region_init_ram(isa_bios, "isa-bios", isa_bios_size);
|
||||
memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size);
|
||||
vmstate_register_ram_global(isa_bios);
|
||||
memory_region_add_subregion_overlap(rom_memory,
|
||||
0x100000 - isa_bios_size,
|
||||
|
|
@ -162,7 +162,7 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
|
|||
goto bios_error;
|
||||
}
|
||||
bios = g_malloc(sizeof(*bios));
|
||||
memory_region_init_ram(bios, "pc.bios", bios_size);
|
||||
memory_region_init_ram(bios, NULL, "pc.bios", bios_size);
|
||||
vmstate_register_ram_global(bios);
|
||||
if (!isapc_ram_fw) {
|
||||
memory_region_set_readonly(bios, true);
|
||||
|
|
@ -183,7 +183,7 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
|
|||
isa_bios_size = 128 * 1024;
|
||||
}
|
||||
isa_bios = g_malloc(sizeof(*isa_bios));
|
||||
memory_region_init_alias(isa_bios, "isa-bios", bios,
|
||||
memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
|
||||
bios_size - isa_bios_size, isa_bios_size);
|
||||
memory_region_add_subregion_overlap(rom_memory,
|
||||
0x100000 - isa_bios_size,
|
||||
|
|
|
|||
|
|
@ -579,7 +579,8 @@ static int pflash_cfi01_init(SysBusDevice *dev)
|
|||
#endif
|
||||
|
||||
memory_region_init_rom_device(
|
||||
&pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
|
||||
&pfl->mem, OBJECT(dev),
|
||||
pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
|
||||
pfl->name, total_len);
|
||||
vmstate_register_ram(&pfl->mem, DEVICE(pfl));
|
||||
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
|
||||
|
|
|
|||
|
|
@ -100,11 +100,11 @@ static void pflash_setup_mappings(pflash_t *pfl)
|
|||
unsigned i;
|
||||
hwaddr size = memory_region_size(&pfl->orig_mem);
|
||||
|
||||
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
|
||||
memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
|
||||
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
|
||||
for (i = 0; i < pfl->mappings; ++i) {
|
||||
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
|
||||
&pfl->orig_mem, 0, size);
|
||||
memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
|
||||
"pflash-alias", &pfl->orig_mem, 0, size);
|
||||
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
|
||||
}
|
||||
}
|
||||
|
|
@ -600,7 +600,7 @@ static int pflash_cfi02_init(SysBusDevice *dev)
|
|||
return NULL;
|
||||
#endif
|
||||
|
||||
memory_region_init_rom_device(&pfl->orig_mem, pfl->be ?
|
||||
memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
|
||||
&pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
|
||||
pfl, pfl->name, chip_len);
|
||||
vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl));
|
||||
|
|
|
|||
|
|
@ -442,7 +442,7 @@ static int cadence_uart_init(SysBusDevice *dev)
|
|||
{
|
||||
UartState *s = FROM_SYSBUS(UartState, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
|
|||
error_propagate(errp, err);
|
||||
return;
|
||||
}
|
||||
memory_region_init_io(&s->io, &debugcon_ops, s,
|
||||
memory_region_init_io(&s->io, OBJECT(dev), &debugcon_ops, s,
|
||||
TYPE_ISA_DEBUGCON_DEVICE, 1);
|
||||
memory_region_add_subregion(isa_address_space_io(d),
|
||||
isa->iobase, &s->io);
|
||||
|
|
|
|||
|
|
@ -96,14 +96,14 @@ typedef struct ChannelState {
|
|||
uint8_t rx, tx;
|
||||
} ChannelState;
|
||||
|
||||
struct SerialState {
|
||||
typedef struct ESCCState {
|
||||
SysBusDevice busdev;
|
||||
struct ChannelState chn[2];
|
||||
uint32_t it_shift;
|
||||
MemoryRegion mmio;
|
||||
uint32_t disabled;
|
||||
uint32_t frequency;
|
||||
};
|
||||
} ESCCState;
|
||||
|
||||
#define SERIAL_CTRL 0
|
||||
#define SERIAL_DATA 1
|
||||
|
|
@ -309,7 +309,7 @@ static void escc_reset_chn(ChannelState *s)
|
|||
|
||||
static void escc_reset(DeviceState *d)
|
||||
{
|
||||
SerialState *s = container_of(d, SerialState, busdev.qdev);
|
||||
ESCCState *s = container_of(d, ESCCState, busdev.qdev);
|
||||
|
||||
escc_reset_chn(&s->chn[0]);
|
||||
escc_reset_chn(&s->chn[1]);
|
||||
|
|
@ -466,7 +466,7 @@ static void escc_update_parameters(ChannelState *s)
|
|||
static void escc_mem_write(void *opaque, hwaddr addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
SerialState *serial = opaque;
|
||||
ESCCState *serial = opaque;
|
||||
ChannelState *s;
|
||||
uint32_t saddr;
|
||||
int newreg, channel;
|
||||
|
|
@ -568,7 +568,7 @@ static void escc_mem_write(void *opaque, hwaddr addr,
|
|||
static uint64_t escc_mem_read(void *opaque, hwaddr addr,
|
||||
unsigned size)
|
||||
{
|
||||
SerialState *serial = opaque;
|
||||
ESCCState *serial = opaque;
|
||||
ChannelState *s;
|
||||
uint32_t saddr;
|
||||
uint32_t ret;
|
||||
|
|
@ -677,7 +677,7 @@ static const VMStateDescription vmstate_escc = {
|
|||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_STRUCT_ARRAY(chn, SerialState, 2, 2, vmstate_escc_chn,
|
||||
VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn,
|
||||
ChannelState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
|
|
@ -689,7 +689,7 @@ MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
|
|||
{
|
||||
DeviceState *dev;
|
||||
SysBusDevice *s;
|
||||
SerialState *d;
|
||||
ESCCState *d;
|
||||
|
||||
dev = qdev_create(NULL, "escc");
|
||||
qdev_prop_set_uint32(dev, "disabled", 0);
|
||||
|
|
@ -707,7 +707,7 @@ MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
|
|||
sysbus_mmio_map(s, 0, base);
|
||||
}
|
||||
|
||||
d = FROM_SYSBUS(SerialState, s);
|
||||
d = FROM_SYSBUS(ESCCState, s);
|
||||
return &d->mmio;
|
||||
}
|
||||
|
||||
|
|
@ -869,7 +869,7 @@ void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
|
|||
|
||||
static int escc_init1(SysBusDevice *dev)
|
||||
{
|
||||
SerialState *s = FROM_SYSBUS(SerialState, dev);
|
||||
ESCCState *s = FROM_SYSBUS(ESCCState, dev);
|
||||
unsigned int i;
|
||||
|
||||
s->chn[0].disabled = s->disabled;
|
||||
|
|
@ -886,7 +886,7 @@ static int escc_init1(SysBusDevice *dev)
|
|||
s->chn[0].otherchn = &s->chn[1];
|
||||
s->chn[1].otherchn = &s->chn[0];
|
||||
|
||||
memory_region_init_io(&s->mmio, &escc_mem_ops, s, "escc",
|
||||
memory_region_init_io(&s->mmio, OBJECT(s), &escc_mem_ops, s, "escc",
|
||||
ESCC_SIZE << s->it_shift);
|
||||
sysbus_init_mmio(dev, &s->mmio);
|
||||
|
||||
|
|
@ -902,13 +902,13 @@ static int escc_init1(SysBusDevice *dev)
|
|||
}
|
||||
|
||||
static Property escc_properties[] = {
|
||||
DEFINE_PROP_UINT32("frequency", SerialState, frequency, 0),
|
||||
DEFINE_PROP_UINT32("it_shift", SerialState, it_shift, 0),
|
||||
DEFINE_PROP_UINT32("disabled", SerialState, disabled, 0),
|
||||
DEFINE_PROP_UINT32("chnBtype", SerialState, chn[0].type, 0),
|
||||
DEFINE_PROP_UINT32("chnAtype", SerialState, chn[1].type, 0),
|
||||
DEFINE_PROP_CHR("chrB", SerialState, chn[0].chr),
|
||||
DEFINE_PROP_CHR("chrA", SerialState, chn[1].chr),
|
||||
DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0),
|
||||
DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0),
|
||||
DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0),
|
||||
DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0),
|
||||
DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0),
|
||||
DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr),
|
||||
DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
|
@ -926,7 +926,7 @@ static void escc_class_init(ObjectClass *klass, void *data)
|
|||
static const TypeInfo escc_info = {
|
||||
.name = "escc",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SerialState),
|
||||
.instance_size = sizeof(ESCCState),
|
||||
.class_init = escc_class_init,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -211,7 +211,8 @@ static int etraxfs_ser_init(SysBusDevice *dev)
|
|||
struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
|
||||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
memory_region_init_io(&s->mmio, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
|
||||
memory_region_init_io(&s->mmio, OBJECT(s), &ser_ops, s,
|
||||
"etraxfs-serial", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->mmio);
|
||||
|
||||
s->chr = qemu_char_get_next_serial();
|
||||
|
|
|
|||
|
|
@ -630,8 +630,8 @@ static int exynos4210_uart_init(SysBusDevice *dev)
|
|||
Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev);
|
||||
|
||||
/* memory mapping */
|
||||
memory_region_init_io(&s->iomem, &exynos4210_uart_ops, s, "exynos4210.uart",
|
||||
EXYNOS4210_UART_REGS_MEM_SIZE);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
|
||||
"exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ static int grlib_apbuart_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &uart->irq);
|
||||
|
||||
memory_region_init_io(&uart->iomem, &grlib_apbuart_ops, uart,
|
||||
memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
|
||||
"uart", UART_REG_SIZE);
|
||||
|
||||
sysbus_init_mmio(dev, &uart->iomem);
|
||||
|
|
|
|||
|
|
@ -386,7 +386,8 @@ static int imx_serial_init(SysBusDevice *dev)
|
|||
IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);
|
||||
|
||||
|
||||
memory_region_init_io(&s->iomem, &imx_serial_ops, s, "imx-serial", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,
|
||||
"imx-serial", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
|
|
|
|||
|
|
@ -250,7 +250,8 @@ static int lm32_uart_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s,
|
||||
"uart", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
s->chr = qemu_char_get_next_serial();
|
||||
|
|
|
|||
|
|
@ -302,6 +302,6 @@ void mcf_uart_mm_init(MemoryRegion *sysmem,
|
|||
mcf_uart_state *s;
|
||||
|
||||
s = mcf_uart_init(irq, chr);
|
||||
memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40);
|
||||
memory_region_init_io(&s->iomem, NULL, &mcf_uart_ops, s, "uart", 0x40);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -196,7 +196,7 @@ static int milkymist_uart_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
|
||||
memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
|
||||
"milkymist-uart", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->regs_region);
|
||||
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
|
|||
struct omap_uart_s *s = omap_uart_init(base, irq,
|
||||
fclk, iclk, txdma, rxdma, label, chr);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap.uart", 0x100);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s, "omap.uart", 0x100);
|
||||
|
||||
s->ta = ta;
|
||||
|
||||
|
|
|
|||
|
|
@ -587,7 +587,7 @@ bool parallel_mm_init(MemoryRegion *address_space,
|
|||
s->it_shift = it_shift;
|
||||
qemu_register_reset(parallel_reset, s);
|
||||
|
||||
memory_region_init_io(&s->iomem, ¶llel_mm_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s,
|
||||
"parallel", 8 << it_shift);
|
||||
memory_region_add_subregion(address_space, base, &s->iomem);
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -265,7 +265,7 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id)
|
|||
{
|
||||
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pl011_ops, s, "pl011", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
s->id = id;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp)
|
|||
serial_realize_core(s, errp);
|
||||
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
|
||||
|
||||
memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
|
||||
memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
|
||||
isa_register_ioport(isadev, &s->io, isa->iobase);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ static int serial_pci_init(PCIDevice *dev)
|
|||
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
|
||||
s->irq = pci->dev.irq[0];
|
||||
|
||||
memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
|
||||
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
|
||||
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -102,7 +102,7 @@ static int multi_serial_pci_init(PCIDevice *dev)
|
|||
assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
|
||||
|
||||
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
|
||||
memory_region_init(&pci->iobar, "multiserial", 8 * pci->ports);
|
||||
memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
|
||||
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
|
||||
pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
|
||||
pci->ports);
|
||||
|
|
@ -118,7 +118,8 @@ static int multi_serial_pci_init(PCIDevice *dev)
|
|||
}
|
||||
s->irq = pci->irqs[i];
|
||||
pci->name[i] = g_strdup_printf("uart #%d", i+1);
|
||||
memory_region_init_io(&s->io, &serial_io_ops, s, pci->name[i], 8);
|
||||
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
|
||||
pci->name[i], 8);
|
||||
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
|
||||
}
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -703,7 +703,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
|
|||
|
||||
vmstate_register(NULL, base, &vmstate_serial, s);
|
||||
|
||||
memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
|
||||
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
|
||||
memory_region_add_subregion(system_io, base, &s->io);
|
||||
|
||||
return s;
|
||||
|
|
@ -766,7 +766,7 @@ SerialState *serial_mm_init(MemoryRegion *address_space,
|
|||
}
|
||||
vmstate_register(NULL, base, &vmstate_serial, s);
|
||||
|
||||
memory_region_init_io(&s->io, &serial_mm_ops[end], s,
|
||||
memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
|
||||
"serial", 8 << it_shift);
|
||||
memory_region_add_subregion(address_space, base, &s->io);
|
||||
|
||||
|
|
|
|||
|
|
@ -383,14 +383,14 @@ void sh_serial_init(MemoryRegion *sysmem,
|
|||
|
||||
sh_serial_clear_fifo(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &sh_serial_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
|
||||
"serial", 0x100000000ULL);
|
||||
|
||||
memory_region_init_alias(&s->iomem_p4, "serial-p4", &s->iomem,
|
||||
memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
|
||||
0, 0x28);
|
||||
memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
|
||||
|
||||
memory_region_init_alias(&s->iomem_a7, "serial-a7", &s->iomem,
|
||||
memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
|
||||
0, 0x28);
|
||||
memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
|
||||
|
||||
|
|
|
|||
|
|
@ -588,17 +588,17 @@ static int tpci200_initfn(PCIDevice *pci_dev)
|
|||
pci_set_long(c + 0x48, 0x00024C06);
|
||||
pci_set_long(c + 0x4C, 0x00000003);
|
||||
|
||||
memory_region_init_io(&s->mmio, &tpci200_cfg_ops,
|
||||
memory_region_init_io(&s->mmio, OBJECT(s), &tpci200_cfg_ops,
|
||||
s, "tpci200_mmio", 128);
|
||||
memory_region_init_io(&s->io, &tpci200_cfg_ops,
|
||||
memory_region_init_io(&s->io, OBJECT(s), &tpci200_cfg_ops,
|
||||
s, "tpci200_io", 128);
|
||||
memory_region_init_io(&s->las0, &tpci200_las0_ops,
|
||||
memory_region_init_io(&s->las0, OBJECT(s), &tpci200_las0_ops,
|
||||
s, "tpci200_las0", 256);
|
||||
memory_region_init_io(&s->las1, &tpci200_las1_ops,
|
||||
memory_region_init_io(&s->las1, OBJECT(s), &tpci200_las1_ops,
|
||||
s, "tpci200_las1", 1024);
|
||||
memory_region_init_io(&s->las2, &tpci200_las2_ops,
|
||||
memory_region_init_io(&s->las2, OBJECT(s), &tpci200_las2_ops,
|
||||
s, "tpci200_las2", 1024*1024*32);
|
||||
memory_region_init_io(&s->las3, &tpci200_las3_ops,
|
||||
memory_region_init_io(&s->las3, OBJECT(s), &tpci200_las3_ops,
|
||||
s, "tpci200_las3", 1024*1024*16);
|
||||
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
|
||||
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
||||
|
|
|
|||
|
|
@ -199,8 +199,8 @@ static int xilinx_uartlite_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
uart_update_status(s);
|
||||
memory_region_init_io(&s->mmio, &uart_ops, s, "xlnx.xps-uartlite",
|
||||
R_MAX * 4);
|
||||
memory_region_init_io(&s->mmio, OBJECT(s), &uart_ops, s,
|
||||
"xlnx.xps-uartlite", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->mmio);
|
||||
|
||||
s->chr = qemu_char_get_next_serial();
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static int empty_slot_init1(SysBusDevice *dev)
|
|||
{
|
||||
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &empty_slot_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
|
||||
"empty-slot", s->size);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -727,6 +727,7 @@ int rom_load_all(void)
|
|||
addr += rom->romsize;
|
||||
section = memory_region_find(get_system_memory(), rom->addr, 1);
|
||||
rom->isrom = int128_nz(section.size) && memory_region_is_rom(section.mr);
|
||||
memory_region_unref(section.mr);
|
||||
}
|
||||
qemu_register_reset(rom_reset, NULL);
|
||||
roms_loaded = 1;
|
||||
|
|
|
|||
|
|
@ -68,7 +68,8 @@ static int a15mp_priv_init(SysBusDevice *dev)
|
|||
* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
|
||||
* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
|
||||
*/
|
||||
memory_region_init(&s->container, "a15mp-priv-container", 0x8000);
|
||||
memory_region_init(&s->container, OBJECT(s),
|
||||
"a15mp-priv-container", 0x8000);
|
||||
memory_region_add_subregion(&s->container, 0x1000,
|
||||
sysbus_mmio_get_region(busdev, 0));
|
||||
memory_region_add_subregion(&s->container, 0x2000,
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ static int a9mp_priv_init(SysBusDevice *dev)
|
|||
*
|
||||
* We should implement the global timer but don't currently do so.
|
||||
*/
|
||||
memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
|
||||
memory_region_init(&s->container, OBJECT(s), "a9mp-priv-container", 0x2000);
|
||||
memory_region_add_subregion(&s->container, 0,
|
||||
sysbus_mmio_get_region(scubusdev, 0));
|
||||
/* GIC CPU interface */
|
||||
|
|
|
|||
|
|
@ -87,8 +87,10 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
|
|||
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
|
||||
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
|
||||
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
|
||||
memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
|
||||
memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
|
||||
memory_region_init(&s->container, OBJECT(s),
|
||||
"mpcode-priv-container", 0x2000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s),
|
||||
&mpcore_scu_ops, s, "mpcore-scu", 0x100);
|
||||
memory_region_add_subregion(&s->container, 0, &s->iomem);
|
||||
/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
|
||||
* at 0x200, 0x300...
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ static void icc_bridge_init(Object *obj)
|
|||
/* Do not change order of registering regions,
|
||||
* APIC must be first registered region, board maps it by 0 index
|
||||
*/
|
||||
memory_region_init(&s->apic_container, "icc-apic-container",
|
||||
memory_region_init(&s->apic_container, obj, "icc-apic-container",
|
||||
APIC_SPACE_SIZE);
|
||||
sysbus_init_mmio(sb, &s->apic_container);
|
||||
s->icc_bus.apic_address_space = &s->apic_container;
|
||||
|
|
|
|||
|
|
@ -269,13 +269,13 @@ void axisdev88_init(QEMUMachineInitArgs *args)
|
|||
env = &cpu->env;
|
||||
|
||||
/* allocate RAM */
|
||||
memory_region_init_ram(phys_ram, "axisdev88.ram", ram_size);
|
||||
memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
|
||||
vmstate_register_ram_global(phys_ram);
|
||||
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
|
||||
|
||||
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
|
||||
internal memory. */
|
||||
memory_region_init_ram(phys_intmem, "axisdev88.chipram", INTMEM_SIZE);
|
||||
memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
|
||||
vmstate_register_ram_global(phys_intmem);
|
||||
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
|
||||
|
||||
|
|
@ -283,13 +283,13 @@ void axisdev88_init(QEMUMachineInitArgs *args)
|
|||
nand = drive_get(IF_MTD, 0, 0);
|
||||
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
|
||||
NAND_MFR_STMICRO, 0x39);
|
||||
memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state,
|
||||
memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
|
||||
"nand", 0x05000000);
|
||||
memory_region_add_subregion(address_space_mem, 0x10000000,
|
||||
&nand_state.iomem);
|
||||
|
||||
gpio_state.nand = &nand_state;
|
||||
memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state,
|
||||
memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
|
||||
"gpio", 0x5c);
|
||||
memory_region_add_subregion(address_space_mem, 0x3001a000,
|
||||
&gpio_state.iomem);
|
||||
|
|
|
|||
|
|
@ -2805,7 +2805,8 @@ static const MemoryRegionOps cirrus_vga_io_ops = {
|
|||
},
|
||||
};
|
||||
|
||||
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
|
||||
static void cirrus_init_common(CirrusVGAState *s, Object *owner,
|
||||
int device_id, int is_pci,
|
||||
MemoryRegion *system_memory,
|
||||
MemoryRegion *system_io)
|
||||
{
|
||||
|
|
@ -2840,21 +2841,22 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
|
|||
}
|
||||
|
||||
/* Register ioport 0x3b0 - 0x3df */
|
||||
memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s,
|
||||
memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
|
||||
"cirrus-io", 0x30);
|
||||
memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
|
||||
|
||||
memory_region_init(&s->low_mem_container,
|
||||
memory_region_init(&s->low_mem_container, owner,
|
||||
"cirrus-lowmem-container",
|
||||
0x20000);
|
||||
|
||||
memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
|
||||
memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
|
||||
"cirrus-low-memory", 0x20000);
|
||||
memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
|
||||
for (i = 0; i < 2; ++i) {
|
||||
static const char *names[] = { "vga.bank0", "vga.bank1" };
|
||||
MemoryRegion *bank = &s->cirrus_bank[i];
|
||||
memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
|
||||
memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
|
||||
0, 0x8000);
|
||||
memory_region_set_enabled(bank, false);
|
||||
memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
|
||||
bank, 1);
|
||||
|
|
@ -2866,13 +2868,13 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
|
|||
memory_region_set_coalescing(&s->low_mem);
|
||||
|
||||
/* I/O handler for LFB */
|
||||
memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
|
||||
memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
|
||||
"cirrus-linear-io", s->vga.vram_size_mb
|
||||
* 1024 * 1024);
|
||||
memory_region_set_flush_coalesced(&s->cirrus_linear_io);
|
||||
|
||||
/* I/O handler for LFB */
|
||||
memory_region_init_io(&s->cirrus_linear_bitblt_io,
|
||||
memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
|
||||
&cirrus_linear_bitblt_io_ops,
|
||||
s,
|
||||
"cirrus-bitblt-mmio",
|
||||
|
|
@ -2880,7 +2882,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
|
|||
memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
|
||||
|
||||
/* I/O handler for memory-mapped I/O */
|
||||
memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
|
||||
memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
|
||||
"cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
|
||||
memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
|
||||
|
||||
|
|
@ -2912,8 +2914,8 @@ static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
|
|||
ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
|
||||
VGACommonState *s = &d->cirrus_vga.vga;
|
||||
|
||||
vga_common_init(s);
|
||||
cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
|
||||
vga_common_init(s, OBJECT(dev));
|
||||
cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
|
||||
isa_address_space(isadev),
|
||||
isa_address_space_io(isadev));
|
||||
s->con = graphic_console_init(dev, s->hw_ops, s);
|
||||
|
|
@ -2958,14 +2960,14 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
|
|||
int16_t device_id = pc->device_id;
|
||||
|
||||
/* setup VGA */
|
||||
vga_common_init(&s->vga);
|
||||
cirrus_init_common(s, device_id, 1, pci_address_space(dev),
|
||||
vga_common_init(&s->vga, OBJECT(dev));
|
||||
cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
|
||||
pci_address_space_io(dev));
|
||||
s->vga.con = graphic_console_init(DEVICE(dev), s->vga.hw_ops, &s->vga);
|
||||
|
||||
/* setup PCI */
|
||||
|
||||
memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
|
||||
memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
|
||||
|
||||
/* XXX: add byte swapping apertures */
|
||||
memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
|
||||
|
|
|
|||
|
|
@ -1126,6 +1126,11 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
|
|||
/* Total number of bytes of virtual screen used by current window */
|
||||
w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
|
||||
(w->rightbot_y - w->lefttop_y + 1);
|
||||
|
||||
/* TODO: add .exit and unref the region there. Not needed yet since sysbus
|
||||
* does not support hot-unplug.
|
||||
*/
|
||||
memory_region_unref(w->mem_section.mr);
|
||||
w->mem_section = memory_region_find(sysbus_address_space(&s->busdev),
|
||||
fb_start_addr, w->fb_len);
|
||||
assert(w->mem_section.mr);
|
||||
|
|
@ -1154,6 +1159,7 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
|
|||
return;
|
||||
|
||||
error_return:
|
||||
memory_region_unref(w->mem_section.mr);
|
||||
w->mem_section.mr = NULL;
|
||||
w->mem_section.size = int128_zero();
|
||||
w->host_fb_addr = NULL;
|
||||
|
|
@ -1902,7 +1908,7 @@ static int exynos4210_fimd_init(SysBusDevice *dev)
|
|||
sysbus_init_irq(dev, &s->irq[1]);
|
||||
sysbus_init_irq(dev, &s->irq[2]);
|
||||
|
||||
memory_region_init_io(&s->iomem, &exynos4210_fimd_mmio_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_fimd_mmio_ops, s,
|
||||
"exynos4210.fimd", FIMD_REGS_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
s->console = graphic_console_init(DEVICE(dev), &exynos4210_fimd_ops, s);
|
||||
|
|
|
|||
|
|
@ -54,11 +54,11 @@ void framebuffer_update_display(
|
|||
src_len = src_width * rows;
|
||||
|
||||
mem_section = memory_region_find(address_space, base, src_len);
|
||||
mem = mem_section.mr;
|
||||
if (int128_get64(mem_section.size) != src_len ||
|
||||
!memory_region_is_ram(mem_section.mr)) {
|
||||
return;
|
||||
goto out;
|
||||
}
|
||||
mem = mem_section.mr;
|
||||
assert(mem);
|
||||
assert(mem_section.offset_within_address_space == base);
|
||||
|
||||
|
|
@ -68,10 +68,10 @@ void framebuffer_update_display(
|
|||
but it's not really worth it as dirty flag tracking will probably
|
||||
already have failed above. */
|
||||
if (!src_base)
|
||||
return;
|
||||
goto out;
|
||||
if (src_len != src_width * rows) {
|
||||
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
|
||||
return;
|
||||
goto out;
|
||||
}
|
||||
src = src_base;
|
||||
dest = surface_data(ds);
|
||||
|
|
@ -102,10 +102,12 @@ void framebuffer_update_display(
|
|||
}
|
||||
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
|
||||
if (first < 0) {
|
||||
return;
|
||||
goto out;
|
||||
}
|
||||
memory_region_reset_dirty(mem, mem_section.offset_within_region, src_len,
|
||||
DIRTY_MEMORY_VGA);
|
||||
*first_row = first;
|
||||
*last_row = last;
|
||||
out:
|
||||
memory_region_unref(mem);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -486,8 +486,8 @@ static void g364fb_init(DeviceState *dev, G364State *s)
|
|||
|
||||
s->con = graphic_console_init(dev, &g364fb_ops, s);
|
||||
|
||||
memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
|
||||
memory_region_init_ram_ptr(&s->mem_vram, "vram",
|
||||
memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
|
||||
memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
|
||||
s->vram_size, s->vram);
|
||||
vmstate_register_ram(&s->mem_vram, dev);
|
||||
memory_region_set_coalescing(&s->mem_vram);
|
||||
|
|
|
|||
|
|
@ -264,7 +264,7 @@ static int jazz_led_init(SysBusDevice *dev)
|
|||
{
|
||||
LedState *s = FROM_SYSBUS(LedState, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &led_ops, s, "led", 1);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &led_ops, s, "led", 1);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
s->con = graphic_console_init(DEVICE(dev), &jazz_led_ops, s);
|
||||
|
|
|
|||
|
|
@ -447,7 +447,7 @@ static int milkymist_tmu2_init(SysBusDevice *dev)
|
|||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
memory_region_init_io(&s->regs_region, &tmu2_mmio_ops, s,
|
||||
memory_region_init_io(&s->regs_region, OBJECT(s), &tmu2_mmio_ops, s,
|
||||
"milkymist-tmu2", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->regs_region);
|
||||
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ static int milkymist_vgafb_init(SysBusDevice *dev)
|
|||
{
|
||||
MilkymistVgafbState *s = FROM_SYSBUS(typeof(*s), dev);
|
||||
|
||||
memory_region_init_io(&s->regs_region, &vgafb_mmio_ops, s,
|
||||
memory_region_init_io(&s->regs_region, OBJECT(s), &vgafb_mmio_ops, s,
|
||||
"milkymist-vgafb", R_MAX * 4);
|
||||
sysbus_init_mmio(dev, &s->regs_region);
|
||||
|
||||
|
|
|
|||
|
|
@ -1053,15 +1053,15 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
|
|||
s->drq = drq;
|
||||
omap_dss_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem_diss1, &omap_diss_ops, s, "omap.diss1",
|
||||
memory_region_init_io(&s->iomem_diss1, NULL, &omap_diss_ops, s, "omap.diss1",
|
||||
omap_l4_region_size(ta, 0));
|
||||
memory_region_init_io(&s->iomem_disc1, &omap_disc_ops, s, "omap.disc1",
|
||||
memory_region_init_io(&s->iomem_disc1, NULL, &omap_disc_ops, s, "omap.disc1",
|
||||
omap_l4_region_size(ta, 1));
|
||||
memory_region_init_io(&s->iomem_rfbi1, &omap_rfbi_ops, s, "omap.rfbi1",
|
||||
memory_region_init_io(&s->iomem_rfbi1, NULL, &omap_rfbi_ops, s, "omap.rfbi1",
|
||||
omap_l4_region_size(ta, 2));
|
||||
memory_region_init_io(&s->iomem_venc1, &omap_venc_ops, s, "omap.venc1",
|
||||
memory_region_init_io(&s->iomem_venc1, NULL, &omap_venc_ops, s, "omap.venc1",
|
||||
omap_l4_region_size(ta, 3));
|
||||
memory_region_init_io(&s->iomem_im3, &omap_im3_ops, s,
|
||||
memory_region_init_io(&s->iomem_im3, NULL, &omap_im3_ops, s,
|
||||
"omap.im3", 0x1000);
|
||||
|
||||
omap_l4_attach(ta, 0, &s->iomem_diss1);
|
||||
|
|
|
|||
|
|
@ -403,7 +403,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
|
|||
s->sysmem = sysmem;
|
||||
omap_lcdc_reset(s);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
s->con = graphic_console_init(NULL, &omap_ops, s);
|
||||
|
|
|
|||
|
|
@ -453,7 +453,7 @@ static int pl110_init(SysBusDevice *dev)
|
|||
{
|
||||
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
|
||||
|
|
|
|||
|
|
@ -1009,7 +1009,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
|
|||
|
||||
pxa2xx_lcdc_orientation(s, graphic_rotate);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
|
||||
memory_region_init_io(&s->iomem, NULL, &pxa2xx_lcdc_ops, s,
|
||||
"pxa2xx-lcd-controller", 0x00100000);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include "qemu-common.h"
|
||||
#include "qemu/timer.h"
|
||||
#include "qemu/queue.h"
|
||||
#include "qemu/atomic.h"
|
||||
#include "monitor/monitor.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "trace.h"
|
||||
|
|
@ -1726,7 +1727,7 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
|
|||
trace_qxl_send_events_vm_stopped(d->id, events);
|
||||
return;
|
||||
}
|
||||
old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
|
||||
old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
|
||||
if ((old_pending & le_events) == le_events) {
|
||||
return;
|
||||
}
|
||||
|
|
@ -1981,18 +1982,20 @@ static int qxl_init_common(PCIQXLDevice *qxl)
|
|||
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
|
||||
|
||||
qxl->rom_size = qxl_rom_size();
|
||||
memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
|
||||
memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
|
||||
qxl->rom_size);
|
||||
vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
|
||||
init_qxl_rom(qxl);
|
||||
init_qxl_ram(qxl);
|
||||
|
||||
qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
|
||||
memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
|
||||
memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
|
||||
qxl->vram_size);
|
||||
vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
|
||||
memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
|
||||
0, qxl->vram32_size);
|
||||
memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
|
||||
&qxl->vram_bar, 0, qxl->vram32_size);
|
||||
|
||||
memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
|
||||
memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
|
||||
"qxl-ioports", io_size);
|
||||
if (qxl->id == 0) {
|
||||
vga_dirty_log_start(&qxl->vga);
|
||||
|
|
@ -2067,9 +2070,11 @@ static int qxl_init_primary(PCIDevice *dev)
|
|||
qxl->id = 0;
|
||||
qxl_init_ramsize(qxl);
|
||||
vga->vram_size_mb = qxl->vga.vram_size >> 20;
|
||||
vga_common_init(vga);
|
||||
vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
|
||||
portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
|
||||
vga_common_init(vga, OBJECT(dev));
|
||||
vga_init(vga, OBJECT(dev),
|
||||
pci_address_space(dev), pci_address_space_io(dev), false);
|
||||
portio_list_init(qxl_vga_port_list, OBJECT(dev), qxl_vga_portio_list,
|
||||
vga, "vga");
|
||||
portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
|
||||
|
||||
vga->con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);
|
||||
|
|
@ -2093,7 +2098,8 @@ static int qxl_init_secondary(PCIDevice *dev)
|
|||
|
||||
qxl->id = device_id++;
|
||||
qxl_init_ramsize(qxl);
|
||||
memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
|
||||
memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
|
||||
qxl->vga.vram_size);
|
||||
vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
|
||||
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
|
||||
qxl->vga.con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);
|
||||
|
|
|
|||
|
|
@ -1408,23 +1408,23 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
|
|||
s->dc_crt_control = 0x00010000;
|
||||
|
||||
/* allocate local memory */
|
||||
memory_region_init_ram(&s->local_mem_region, "sm501.local",
|
||||
memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
|
||||
local_mem_bytes);
|
||||
vmstate_register_ram_global(&s->local_mem_region);
|
||||
s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
|
||||
memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
|
||||
|
||||
/* map mmio */
|
||||
memory_region_init_io(sm501_system_config, &sm501_system_config_ops, s,
|
||||
memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops, s,
|
||||
"sm501-system-config", 0x6c);
|
||||
memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
|
||||
sm501_system_config);
|
||||
memory_region_init_io(sm501_disp_ctrl, &sm501_disp_ctrl_ops, s,
|
||||
memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
|
||||
"sm501-disp-ctrl", 0x1000);
|
||||
memory_region_add_subregion(address_space_mem,
|
||||
base + MMIO_BASE_OFFSET + SM501_DC,
|
||||
sm501_disp_ctrl);
|
||||
memory_region_init_io(sm501_2d_engine, &sm501_2d_engine_ops, s,
|
||||
memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s,
|
||||
"sm501-2d-engine", 0x54);
|
||||
memory_region_add_subregion(address_space_mem,
|
||||
base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
|
||||
|
|
|
|||
|
|
@ -578,10 +578,10 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
|
|||
nand = drive_get(IF_MTD, 0, 0);
|
||||
s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
|
||||
|
||||
memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
|
||||
memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
|
||||
memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000);
|
||||
vmstate_register_ram_global(&s->vram);
|
||||
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
|
||||
memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
|
||||
|
|
|
|||
|
|
@ -528,7 +528,7 @@ static int tcx_init1(SysBusDevice *dev)
|
|||
int size;
|
||||
uint8_t *vram_base;
|
||||
|
||||
memory_region_init_ram(&s->vram_mem, "tcx.vram",
|
||||
memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
|
||||
s->vram_size * (1 + 4 + 4));
|
||||
vmstate_register_ram_global(&s->vram_mem);
|
||||
vram_base = memory_region_get_ram_ptr(&s->vram_mem);
|
||||
|
|
@ -536,21 +536,23 @@ static int tcx_init1(SysBusDevice *dev)
|
|||
/* 8-bit plane */
|
||||
s->vram = vram_base;
|
||||
size = s->vram_size;
|
||||
memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
|
||||
memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
|
||||
&s->vram_mem, vram_offset, size);
|
||||
sysbus_init_mmio(dev, &s->vram_8bit);
|
||||
vram_offset += size;
|
||||
vram_base += size;
|
||||
|
||||
/* DAC */
|
||||
memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
|
||||
memory_region_init_io(&s->dac, OBJECT(s), &tcx_dac_ops, s,
|
||||
"tcx.dac", TCX_DAC_NREGS);
|
||||
sysbus_init_mmio(dev, &s->dac);
|
||||
|
||||
/* TEC (dummy) */
|
||||
memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
|
||||
memory_region_init_io(&s->tec, OBJECT(s), &dummy_ops, s,
|
||||
"tcx.tec", TCX_TEC_NREGS);
|
||||
sysbus_init_mmio(dev, &s->tec);
|
||||
/* THC: NetBSD writes here even with 8-bit display: dummy */
|
||||
memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
|
||||
memory_region_init_io(&s->thc24, OBJECT(s), &dummy_ops, s, "tcx.thc24",
|
||||
TCX_THC_NREGS_24);
|
||||
sysbus_init_mmio(dev, &s->thc24);
|
||||
|
||||
|
|
@ -559,7 +561,7 @@ static int tcx_init1(SysBusDevice *dev)
|
|||
size = s->vram_size * 4;
|
||||
s->vram24 = (uint32_t *)vram_base;
|
||||
s->vram24_offset = vram_offset;
|
||||
memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
|
||||
memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
|
||||
&s->vram_mem, vram_offset, size);
|
||||
sysbus_init_mmio(dev, &s->vram_24bit);
|
||||
vram_offset += size;
|
||||
|
|
@ -569,14 +571,14 @@ static int tcx_init1(SysBusDevice *dev)
|
|||
size = s->vram_size * 4;
|
||||
s->cplane = (uint32_t *)vram_base;
|
||||
s->cplane_offset = vram_offset;
|
||||
memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
|
||||
memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
|
||||
&s->vram_mem, vram_offset, size);
|
||||
sysbus_init_mmio(dev, &s->vram_cplane);
|
||||
|
||||
s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s);
|
||||
} else {
|
||||
/* THC 8 bit (dummy) */
|
||||
memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
|
||||
memory_region_init_io(&s->thc8, OBJECT(s), &dummy_ops, s, "tcx.thc8",
|
||||
TCX_THC_NREGS_8);
|
||||
sysbus_init_mmio(dev, &s->thc8);
|
||||
|
||||
|
|
|
|||
|
|
@ -105,13 +105,13 @@ static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base,
|
|||
|
||||
s->it_shift = it_shift;
|
||||
s_ioport_ctrl = g_malloc(sizeof(*s_ioport_ctrl));
|
||||
memory_region_init_io(s_ioport_ctrl, &vga_mm_ctrl_ops, s,
|
||||
memory_region_init_io(s_ioport_ctrl, NULL, &vga_mm_ctrl_ops, s,
|
||||
"vga-mm-ctrl", 0x100000);
|
||||
memory_region_set_flush_coalesced(s_ioport_ctrl);
|
||||
|
||||
vga_io_memory = g_malloc(sizeof(*vga_io_memory));
|
||||
/* XXX: endianness? */
|
||||
memory_region_init_io(vga_io_memory, &vga_mem_ops, &s->vga,
|
||||
memory_region_init_io(vga_io_memory, NULL, &vga_mem_ops, &s->vga,
|
||||
"vga-mem", 0x20000);
|
||||
|
||||
vmstate_register(NULL, 0, &vmstate_vga_common, s);
|
||||
|
|
@ -132,11 +132,11 @@ int isa_vga_mm_init(hwaddr vram_base,
|
|||
s = g_malloc0(sizeof(*s));
|
||||
|
||||
s->vga.vram_size_mb = VGA_RAM_SIZE >> 20;
|
||||
vga_common_init(&s->vga);
|
||||
vga_common_init(&s->vga, NULL);
|
||||
vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
|
||||
|
||||
s->vga.con = graphic_console_init(NULL, s->vga.hw_ops, s);
|
||||
|
||||
vga_init_vbe(&s->vga, address_space);
|
||||
vga_init_vbe(&s->vga, NULL, address_space);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,9 +56,9 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp)
|
|||
MemoryRegion *vga_io_memory;
|
||||
const MemoryRegionPortio *vga_ports, *vbe_ports;
|
||||
|
||||
vga_common_init(s);
|
||||
vga_common_init(s, OBJECT(dev));
|
||||
s->legacy_address_space = isa_address_space(isadev);
|
||||
vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
|
||||
vga_io_memory = vga_init_io(s, OBJECT(dev), &vga_ports, &vbe_ports);
|
||||
isa_register_portio_list(isadev, 0x3b0, vga_ports, s, "vga");
|
||||
if (vbe_ports) {
|
||||
isa_register_portio_list(isadev, 0x1ce, vbe_ports, s, "vbe");
|
||||
|
|
@ -69,7 +69,7 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp)
|
|||
memory_region_set_coalescing(vga_io_memory);
|
||||
s->con = graphic_console_init(DEVICE(dev), s->hw_ops, s);
|
||||
|
||||
vga_init_vbe(s, isa_address_space(isadev));
|
||||
vga_init_vbe(s, OBJECT(dev), isa_address_space(isadev));
|
||||
/* ROM BIOS */
|
||||
rom_add_vga(VGABIOS_FILENAME);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -147,8 +147,9 @@ static int pci_std_vga_initfn(PCIDevice *dev)
|
|||
VGACommonState *s = &d->vga;
|
||||
|
||||
/* vga + console init */
|
||||
vga_common_init(s);
|
||||
vga_init(s, pci_address_space(dev), pci_address_space_io(dev), true);
|
||||
vga_common_init(s, OBJECT(dev));
|
||||
vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
|
||||
true);
|
||||
|
||||
s->con = graphic_console_init(DEVICE(dev), s->hw_ops, s);
|
||||
|
||||
|
|
@ -157,10 +158,10 @@ static int pci_std_vga_initfn(PCIDevice *dev)
|
|||
|
||||
/* mmio bar for vga register access */
|
||||
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
|
||||
memory_region_init(&d->mmio, "vga.mmio", 4096);
|
||||
memory_region_init_io(&d->ioport, &pci_vga_ioport_ops, d,
|
||||
memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
|
||||
memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
|
||||
"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
|
||||
memory_region_init_io(&d->bochs, &pci_vga_bochs_ops, d,
|
||||
memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
|
||||
"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
|
||||
|
||||
memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
|
||||
|
|
@ -172,7 +173,7 @@ static int pci_std_vga_initfn(PCIDevice *dev)
|
|||
|
||||
if (!dev->rom_bar) {
|
||||
/* compatibility with pc-0.13 and older */
|
||||
vga_init_vbe(s, pci_address_space(dev));
|
||||
vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -198,7 +198,8 @@ static void vga_update_memory_access(VGACommonState *s)
|
|||
}
|
||||
base += isa_mem_base;
|
||||
region = g_malloc(sizeof(*region));
|
||||
memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
|
||||
memory_region_init_alias(region, memory_region_owner(&s->vram),
|
||||
"vga.chain4", &s->vram, offset, size);
|
||||
memory_region_add_subregion_overlap(s->legacy_address_space, base,
|
||||
region, 2);
|
||||
s->chain4_alias = region;
|
||||
|
|
@ -2256,7 +2257,7 @@ static const GraphicHwOps vga_ops = {
|
|||
.text_update = vga_update_text,
|
||||
};
|
||||
|
||||
void vga_common_init(VGACommonState *s)
|
||||
void vga_common_init(VGACommonState *s, Object *obj)
|
||||
{
|
||||
int i, j, v, b;
|
||||
|
||||
|
|
@ -2292,7 +2293,7 @@ void vga_common_init(VGACommonState *s)
|
|||
s->vram_size_mb = s->vram_size >> 20;
|
||||
|
||||
s->is_vbe_vmstate = 1;
|
||||
memory_region_init_ram(&s->vram, "vga.vram", s->vram_size);
|
||||
memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size);
|
||||
vmstate_register_ram_global(&s->vram);
|
||||
xen_register_framebuffer(&s->vram);
|
||||
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
|
||||
|
|
@ -2333,7 +2334,7 @@ static const MemoryRegionPortio vbe_portio_list[] = {
|
|||
};
|
||||
|
||||
/* Used by both ISA and PCI */
|
||||
MemoryRegion *vga_init_io(VGACommonState *s,
|
||||
MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
|
||||
const MemoryRegionPortio **vga_ports,
|
||||
const MemoryRegionPortio **vbe_ports)
|
||||
{
|
||||
|
|
@ -2343,14 +2344,14 @@ MemoryRegion *vga_init_io(VGACommonState *s,
|
|||
*vbe_ports = vbe_portio_list;
|
||||
|
||||
vga_mem = g_malloc(sizeof(*vga_mem));
|
||||
memory_region_init_io(vga_mem, &vga_mem_ops, s,
|
||||
memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
|
||||
"vga-lowmem", 0x20000);
|
||||
memory_region_set_flush_coalesced(vga_mem);
|
||||
|
||||
return vga_mem;
|
||||
}
|
||||
|
||||
void vga_init(VGACommonState *s, MemoryRegion *address_space,
|
||||
void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
|
||||
MemoryRegion *address_space_io, bool init_vga_ports)
|
||||
{
|
||||
MemoryRegion *vga_io_memory;
|
||||
|
|
@ -2364,28 +2365,28 @@ void vga_init(VGACommonState *s, MemoryRegion *address_space,
|
|||
|
||||
s->legacy_address_space = address_space;
|
||||
|
||||
vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
|
||||
vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
|
||||
memory_region_add_subregion_overlap(address_space,
|
||||
isa_mem_base + 0x000a0000,
|
||||
vga_io_memory,
|
||||
1);
|
||||
memory_region_set_coalescing(vga_io_memory);
|
||||
if (init_vga_ports) {
|
||||
portio_list_init(vga_port_list, vga_ports, s, "vga");
|
||||
portio_list_init(vga_port_list, obj, vga_ports, s, "vga");
|
||||
portio_list_add(vga_port_list, address_space_io, 0x3b0);
|
||||
}
|
||||
if (vbe_ports) {
|
||||
portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
|
||||
portio_list_init(vbe_port_list, obj, vbe_ports, s, "vbe");
|
||||
portio_list_add(vbe_port_list, address_space_io, 0x1ce);
|
||||
}
|
||||
}
|
||||
|
||||
void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
|
||||
void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
|
||||
{
|
||||
/* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
|
||||
* so use an alias to avoid double-mapping the same region.
|
||||
*/
|
||||
memory_region_init_alias(&s->vram_vbe, "vram.vbe",
|
||||
memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
|
||||
&s->vram, 0, memory_region_size(&s->vram));
|
||||
/* XXX: use optimized standard vga accesses */
|
||||
memory_region_add_subregion(system_memory,
|
||||
|
|
|
|||
|
|
@ -177,10 +177,10 @@ static inline int c6_to_8(int v)
|
|||
return (v << 2) | (b << 1) | b;
|
||||
}
|
||||
|
||||
void vga_common_init(VGACommonState *s);
|
||||
void vga_init(VGACommonState *s, MemoryRegion *address_space,
|
||||
void vga_common_init(VGACommonState *s, Object *obj);
|
||||
void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
|
||||
MemoryRegion *address_space_io, bool init_vga_ports);
|
||||
MemoryRegion *vga_init_io(VGACommonState *s,
|
||||
MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
|
||||
const MemoryRegionPortio **vga_ports,
|
||||
const MemoryRegionPortio **vbe_ports);
|
||||
void vga_common_reset(VGACommonState *s);
|
||||
|
|
@ -198,7 +198,7 @@ void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
|
|||
|
||||
int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
|
||||
|
||||
void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
|
||||
void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *address_space);
|
||||
uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
|
||||
void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
|
||||
void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);
|
||||
|
|
|
|||
|
|
@ -1194,12 +1194,12 @@ static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
|
|||
s->vga.con = graphic_console_init(dev, &vmsvga_ops, s);
|
||||
|
||||
s->fifo_size = SVGA_FIFO_SIZE;
|
||||
memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
|
||||
memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size);
|
||||
vmstate_register_ram_global(&s->fifo_ram);
|
||||
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
|
||||
|
||||
vga_common_init(&s->vga);
|
||||
vga_init(&s->vga, address_space, io, true);
|
||||
vga_common_init(&s->vga, OBJECT(dev));
|
||||
vga_init(&s->vga, OBJECT(dev), address_space, io, true);
|
||||
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
|
||||
s->new_depth = 32;
|
||||
}
|
||||
|
|
@ -1241,6 +1241,10 @@ static const MemoryRegionOps vmsvga_io_ops = {
|
|||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
.unaligned = true,
|
||||
},
|
||||
.impl = {
|
||||
.unaligned = true,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1253,7 +1257,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
|
|||
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
|
||||
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
|
||||
|
||||
memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
|
||||
memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
|
||||
"vmsvga-io", 0x10);
|
||||
memory_region_set_flush_coalesced(&s->io_bar);
|
||||
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
||||
|
|
@ -1268,7 +1272,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
|
|||
|
||||
if (!dev->rom_bar) {
|
||||
/* compatibility with pc-0.13 and older */
|
||||
vga_init_vbe(&s->chip.vga, pci_address_space(dev));
|
||||
vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -773,7 +773,7 @@ void *etraxfs_dmac_init(hwaddr base, int nr_channels)
|
|||
ctrl->nr_channels = nr_channels;
|
||||
ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels);
|
||||
|
||||
memory_region_init_io(&ctrl->mmio, &dma_ops, ctrl, "etraxfs-dma",
|
||||
memory_region_init_io(&ctrl->mmio, NULL, &dma_ops, ctrl, "etraxfs-dma",
|
||||
nr_channels * 0x2000);
|
||||
memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio);
|
||||
|
||||
|
|
|
|||
|
|
@ -124,16 +124,24 @@ static const VMStateDescription vmstate_isa_i82374 = {
|
|||
},
|
||||
};
|
||||
|
||||
static const MemoryRegionPortio i82374_portio_list[] = {
|
||||
{ 0x0A, 1, 1, .read = i82374_read_isr, },
|
||||
{ 0x10, 8, 1, .write = i82374_write_command, },
|
||||
{ 0x18, 8, 1, .read = i82374_read_status, },
|
||||
{ 0x20, 0x20, 1,
|
||||
.write = i82374_write_descriptor, .read = i82374_read_descriptor, },
|
||||
PORTIO_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void i82374_isa_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
ISAi82374State *isa = I82374(dev);
|
||||
I82374State *s = &isa->state;
|
||||
PortioList *port_list = g_new(PortioList, 1);
|
||||
|
||||
register_ioport_read(isa->iobase + 0x0A, 1, 1, i82374_read_isr, s);
|
||||
register_ioport_write(isa->iobase + 0x10, 8, 1, i82374_write_command, s);
|
||||
register_ioport_read(isa->iobase + 0x18, 8, 1, i82374_read_status, s);
|
||||
register_ioport_write(isa->iobase + 0x20, 0x20, 1, i82374_write_descriptor, s);
|
||||
register_ioport_read(isa->iobase + 0x20, 0x20, 1, i82374_read_descriptor, s);
|
||||
portio_list_init(port_list, OBJECT(isa), i82374_portio_list, s, "i82374");
|
||||
portio_list_add(port_list, isa_address_space_io(&isa->parent_obj),
|
||||
isa->iobase);
|
||||
|
||||
i82374_realize(s, errp);
|
||||
|
||||
|
|
|
|||
|
|
@ -523,7 +523,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
|
|||
d->dshift = dshift;
|
||||
d->cpu_request_exit = cpu_request_exit;
|
||||
|
||||
memory_region_init_io(&d->channel_io, &channel_io_ops, d,
|
||||
memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
|
||||
"dma-chan", 8 << d->dshift);
|
||||
memory_region_add_subregion(isa_address_space_io(NULL),
|
||||
base, &d->channel_io);
|
||||
|
|
@ -535,7 +535,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
|
|||
"dma-pageh");
|
||||
}
|
||||
|
||||
memory_region_init_io(&d->cont_io, &cont_io_ops, d, "dma-cont",
|
||||
memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
|
||||
8 << d->dshift);
|
||||
memory_region_add_subregion(isa_address_space_io(NULL),
|
||||
base + (8 << d->dshift), &d->cont_io);
|
||||
|
|
|
|||
|
|
@ -1663,7 +1663,7 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
|
|||
omap_dma_reset(s->dma);
|
||||
omap_dma_clk_update(s, 0, 1);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
mpu->drq = s->dma->drq;
|
||||
|
|
@ -2085,7 +2085,7 @@ struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
|
|||
omap_dma_reset(s->dma);
|
||||
omap_dma_clk_update(s, 0, !!s->dma->freq);
|
||||
|
||||
memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000);
|
||||
memory_region_init_io(&s->iomem, NULL, &omap_dma4_ops, s, "omap.dma4", 0x1000);
|
||||
memory_region_add_subregion(sysmem, base, &s->iomem);
|
||||
|
||||
mpu->drq = s->dma->drq;
|
||||
|
|
|
|||
|
|
@ -359,7 +359,7 @@ static int pl08x_init(SysBusDevice *dev, int nchannels)
|
|||
{
|
||||
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &pl080_ops, s, "pl080", 0x1000);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
s->nchannels = nchannels;
|
||||
|
|
|
|||
|
|
@ -1528,7 +1528,8 @@ static void pl330_realize(DeviceState *dev, Error **errp)
|
|||
PL330State *s = PL330(dev);
|
||||
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort);
|
||||
memory_region_init_io(&s->iomem, &pl330_ops, s, "dma", PL330_IOMEM_SIZE);
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s,
|
||||
"dma", PL330_IOMEM_SIZE);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
||||
|
||||
s->timer = qemu_new_timer_ns(vm_clock, pl330_exec_cycle_timer, s);
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ static int puv3_dma_init(SysBusDevice *dev)
|
|||
s->reg_CFG[i] = 0x0;
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
|
||||
PUV3_REGS_OFFSET);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
|
|||
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Reference in New Issue