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target/riscv: rvv-1.0: remove integer extract instruction 

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-59-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:44 +08:00 committed by Alistair Francis
parent e29c5cefd8
commit c3536f2f55
2 changed files with 0 additions and 24 deletions
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1
target/riscv/insn32.decode
View File

@ -632,7 +632,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm

23
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -2840,8 +2840,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
*** Vector Permutation Instructions
*/
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
int ofs, int sew, bool sign)
{
@ -2941,27 +2939,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
{
TCGv_i64 tmp = tcg_temp_new_i64();
TCGv dest = dest_gpr(s, a->rd);
if (a->rs1 == 0) {
/* Special case vmv.x.s rd, vs2. */
vec_element_loadi(s, tmp, a->rs2, 0, false);
} else {
/* This instruction ignores LMUL and vector register groups */
int vlmax = s->vlen >> (3 + s->sew);
vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
}
tcg_gen_trunc_i64_tl(dest, tmp);
gen_set_gpr(s, a->rd, dest);
tcg_temp_free_i64(tmp);
return true;
}
/* Integer Scalar Move Instruction */
static void store_element(TCGv_i64 val, TCGv_ptr base,