From f822b7e497fa6a662094b491f86441015f363362 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 19 Jul 2015 10:02:37 +0300 Subject: [PATCH 1/5] target-xtensa: add window overflow check to L32E/S32E Despite L32E and S32E primary use is for window underflow and overflow exception handlers they are just normal instructions, and thus need to check for window overflow. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov --- target-xtensa/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index fda91b7e5d..1349d2f3da 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1943,7 +1943,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) switch (OP2) { case 0: /*L32E*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { + if (gen_check_privilege(dc) && + gen_window_check2(dc, RRR_S, RRR_T)) { TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_addi_i32(addr, cpu_R[RRR_S], (0xffffffc0 | (RRR_R << 2))); @@ -1954,7 +1955,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 4: /*S32E*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { + if (gen_check_privilege(dc) && + gen_window_check2(dc, RRR_S, RRR_T)) { TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_addi_i32(addr, cpu_R[RRR_S], (0xffffffc0 | (RRR_R << 2))); From 5577e57b078a118595071241aba6dac8725a7640 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 21 Sep 2015 20:37:07 +0300 Subject: [PATCH 2/5] target-xtensa: use CPU_LOG_MMU for MMU event logging Signed-off-by: Max Filippov --- target-xtensa/helper.c | 8 ++++---- target-xtensa/op_helper.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 76be50d09c..2c3447ba6b 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -541,8 +541,8 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, wi = ++env->autorefill_idx & 0x3; xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); env->sregs[EXCVADDR] = vaddr; - qemu_log("%s: autorefill(%08x): %08x -> %08x\n", - __func__, vaddr, vpn, pte); + qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", + __func__, vaddr, vpn, pte); } else { xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); entry = &tmp_entry; @@ -590,8 +590,8 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, &paddr, &page_size, &access, false); - qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__, - vaddr, ret ? ~0 : paddr); + qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n", + __func__, vaddr, ret ? ~0 : paddr); if (ret == 0) { *pte = ldl_phys(cs->as, paddr); diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index be657e615d..718e54e7b5 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -57,8 +57,8 @@ void tlb_fill(CPUState *cs, int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, &paddr, &page_size, &access); - qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, - vaddr, is_write, mmu_idx, paddr, ret); + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", + __func__, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { tlb_set_page(cs, From 68931a4082812f56657b39168e815c48f0ab0a8c Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 27 Sep 2015 18:21:19 +0300 Subject: [PATCH 3/5] target-xtensa: xtfpga: attach FLASH to system IO XTFPGA FLASH is tied to XTFPGA system IO block. It's not very important for systems with MMU where system IO block is visible at single location, but it's important for noMMU systems, where system IO block is accessible through two separate physical address ranges. Map XTFPGA FLASH to system IO block and fix offsets used for mapping. Create and initialize FLASH device with series of qdev_prop_set_* as that's the preferred interface now. Keep initialization in a separate function. Signed-off-by: Max Filippov Reviewed-by: Peter Crosthwaite --- hw/xtensa/xtfpga.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 72350f1418..c1bc5aef53 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -149,6 +149,28 @@ static void lx60_net_init(MemoryRegion *address_space, memory_region_add_subregion(address_space, buffers, ram); } +static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, + const LxBoardDesc *board, + DriveInfo *dinfo, int be) +{ + SysBusDevice *s; + DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); + + qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), + &error_abort); + qdev_prop_set_uint32(dev, "num-blocks", + board->flash_size / board->flash_sector_size); + qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_bit(dev, "big-endian", be); + qdev_prop_set_string(dev, "name", "lx60.io.flash"); + qdev_init_nofail(dev); + s = SYS_BUS_DEVICE(dev); + memory_region_add_subregion(address_space, board->flash_base, + sysbus_mmio_get_region(s, 0)); + return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); +} + static uint64_t translate_phys_addr(void *opaque, uint64_t addr) { XtensaCPU *cpu = opaque; @@ -247,16 +269,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine) dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { - flash = pflash_cfi01_register(board->flash_base, - NULL, "lx60.io.flash", board->flash_size, - blk_by_legacy_dinfo(dinfo), - board->flash_sector_size, - board->flash_size / board->flash_sector_size, - 4, 0x0000, 0x0000, 0x0000, 0x0000, be); - if (flash == NULL) { - error_report("unable to mount pflash"); - exit(EXIT_FAILURE); - } + flash = xtfpga_flash_init(system_io, board, dinfo, be); } /* Use presence of kernel file name as 'boot from SRAM' switch. */ @@ -386,7 +399,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine) static void xtensa_lx60_init(MachineState *machine) { static const LxBoardDesc lx60_board = { - .flash_base = 0xf8000000, + .flash_base = 0x08000000, .flash_size = 0x00400000, .flash_sector_size = 0x10000, .sram_size = 0x20000, @@ -397,7 +410,7 @@ static void xtensa_lx60_init(MachineState *machine) static void xtensa_lx200_init(MachineState *machine) { static const LxBoardDesc lx200_board = { - .flash_base = 0xf8000000, + .flash_base = 0x08000000, .flash_size = 0x01000000, .flash_sector_size = 0x20000, .sram_size = 0x2000000, @@ -408,7 +421,7 @@ static void xtensa_lx200_init(MachineState *machine) static void xtensa_ml605_init(MachineState *machine) { static const LxBoardDesc ml605_board = { - .flash_base = 0xf8000000, + .flash_base = 0x08000000, .flash_size = 0x01000000, .flash_sector_size = 0x20000, .sram_size = 0x2000000, @@ -419,7 +432,7 @@ static void xtensa_ml605_init(MachineState *machine) static void xtensa_kc705_init(MachineState *machine) { static const LxBoardDesc kc705_board = { - .flash_base = 0xf0000000, + .flash_base = 0x00000000, .flash_size = 0x08000000, .flash_boot_base = 0x06000000, .flash_sector_size = 0x20000, From 5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 12 Jul 2015 02:10:17 +0300 Subject: [PATCH 4/5] target-xtensa: implement depbits instruction This option provides an instruction for depositing a bit field from the least significant position of one register to an arbitrary position in another register. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 1 + target-xtensa/overlay_tool.h | 5 +++++ target-xtensa/translate.c | 20 ++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 006bcb78b8..15ce0107d6 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -64,6 +64,7 @@ enum { XTENSA_OPTION_MP_SYNCHRO, XTENSA_OPTION_CONDITIONAL_STORE, XTENSA_OPTION_ATOMCTL, + XTENSA_OPTION_DEPBITS, /* Interrupts and exceptions */ XTENSA_OPTION_EXCEPTION, diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index eda03aaca9..e8a7fda3d8 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -30,6 +30,10 @@ { .targno = (no), .type = (typ), .group = (grp), .size = (sz) }, #define XTREG_END { .targno = -1 }, +#ifndef XCHAL_HAVE_DEPBITS +#define XCHAL_HAVE_DEPBITS 0 +#endif + #ifndef XCHAL_HAVE_DIV32 #define XCHAL_HAVE_DIV32 0 #endif @@ -69,6 +73,7 @@ XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \ XTENSA_OPTION_ATOMCTL) | \ + XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ /* Interrupts and exceptions */ \ XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1349d2f3da..be5eb25627 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1972,6 +1972,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 10: /*FP0*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); switch (OP2) { case 0: /*ADD.Sf*/ @@ -2106,6 +2116,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 11: /*FP1*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2 + 16, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); #define gen_compare(rel, br, a, b) \ From 19b7bec4a37b081ed326293148fd793f04896b59 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 19 Jul 2015 09:49:00 +0300 Subject: [PATCH 5/5] target-xtensa: implement S32NB S32NB provides the same functionality as S32I with two exceptions. First, when its operation leaves the processor, the external transaction is marked Non-Bufferable. Second, it may not be used to write to Instruction RAM. In QEMU S32NB is equivalent to S32I. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index be5eb25627..aa0c527dc4 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1965,6 +1965,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } break; + case 5: /*S32N*/ + if (gen_window_check2(dc, RRI4_S, RRI4_T)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); + tcg_temp_free(addr); + } + break; + default: RESERVED(); break;