mirror of https://github.com/xemu-project/xemu.git
hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
The v7-A cluster is specific to the Aspeed 2600 series, remove it from the common AspeedSoCState. The ARM cores belong to the MP cluster, but the array is currently used by TYPE_ASPEED2600_SOC. We'll clean that soon, but for now keep it in Aspeed2600SoCState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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a0c2103070
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c17fc02571
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@ -137,13 +137,15 @@ static const int aspeed_soc_ast2600_irqmap[] = {
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static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
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{
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Aspeed2600SoCState *a = ASPEED2600_SOC(s);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
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return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
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}
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static void aspeed_soc_ast2600_init(Object *obj)
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{
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Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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@ -155,7 +157,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
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}
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for (i = 0; i < sc->num_cpus; i++) {
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object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
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object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
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}
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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@ -169,7 +171,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key");
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object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
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object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
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TYPE_A15MPCORE_PRIV);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
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@ -277,6 +279,7 @@ static uint64_t aspeed_calc_affinity(int cpu)
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static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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{
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int i;
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Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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Error *err = NULL;
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@ -306,39 +309,39 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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/* CPU */
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for (i = 0; i < sc->num_cpus; i++) {
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if (sc->num_cpus > 1) {
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object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
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object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
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ASPEED_A7MPCORE_ADDR, &error_abort);
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}
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object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
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object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
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aspeed_calc_affinity(i), &error_abort);
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object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
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object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
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object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
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object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
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&error_abort);
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object_property_set_link(OBJECT(&s->cpu[i]), "memory",
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object_property_set_link(OBJECT(&a->cpu[i]), "memory",
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OBJECT(s->memory), &error_abort);
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if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
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if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
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return;
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}
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}
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/* A7MPCORE */
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object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
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object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
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&error_abort);
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object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
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object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
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ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
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&error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
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sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
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for (i = 0; i < sc->num_cpus; i++) {
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
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DeviceState *d = DEVICE(&s->cpu[i]);
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SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
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DeviceState *d = DEVICE(&a->cpu[i]);
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irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
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sysbus_connect_irq(sbd, i, irq);
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@ -351,7 +354,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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}
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/* SRAM */
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sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
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sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
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memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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@ -413,7 +416,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
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for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
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irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
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sc->irqmap[ASPEED_DEV_I2C] + i);
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/* The AST2600 I2C controller has one IRQ per bus. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
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@ -579,19 +582,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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* offset 0.
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*/
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
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qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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qdev_get_gpio_in(DEVICE(&a->a7mpcore),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
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qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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qdev_get_gpio_in(DEVICE(&a->a7mpcore),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
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qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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qdev_get_gpio_in(DEVICE(&a->a7mpcore),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
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qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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qdev_get_gpio_in(DEVICE(&a->a7mpcore),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
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/* HACE */
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@ -611,7 +614,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
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for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
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irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
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sc->irqmap[ASPEED_DEV_I3C] + i);
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/* The AST2600 I3C controller has one IRQ per bus. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
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@ -27,7 +27,7 @@ struct Fby35State {
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MemoryRegion bic_memory;
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Clock *bic_sysclk;
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AspeedSoCState bmc;
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Aspeed2600SoCState bmc;
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Aspeed10x0SoCState bic;
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bool mmio_exec;
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@ -70,7 +70,10 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
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static void fby35_bmc_init(Fby35State *s)
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{
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AspeedSoCState *soc;
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object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
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soc = ASPEED_SOC(&s->bmc);
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memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
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UINT64_MAX);
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@ -87,22 +90,21 @@ static void fby35_bmc_init(Fby35State *s)
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&error_abort);
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object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
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&error_abort);
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aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
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aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
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qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
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aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
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aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
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/* Install first FMC flash content as a boot rom. */
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if (!s->mmio_exec) {
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DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
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if (mtd0) {
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AspeedSoCState *bmc = &s->bmc;
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uint64_t rom_size = memory_region_size(&bmc->spi_boot);
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uint64_t rom_size = memory_region_size(&soc->spi_boot);
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memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
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rom_size, &error_abort);
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memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
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memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
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&s->bmc_boot_rom, 1);
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fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
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@ -50,7 +50,6 @@ struct AspeedSoCState {
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DeviceState parent;
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ARMCPU cpu[ASPEED_CPUS_NUM];
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A15MPPrivState a7mpcore;
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MemoryRegion *memory;
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MemoryRegion *dram_mr;
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MemoryRegion dram_container;
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@ -107,6 +106,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
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struct Aspeed2600SoCState {
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AspeedSoCState parent;
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A15MPPrivState a7mpcore;
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ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
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};
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#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
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