From c16bfd84fd8b88798a0235c12f4528803a55a7bf Mon Sep 17 00:00:00 2001 From: Matt Borgerson Date: Fri, 20 Jun 2025 16:07:02 -0700 Subject: [PATCH] nvnet: Check for dma disable before tx/rx --- hw/xbox/mcpx/nvnet/nvnet.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/xbox/mcpx/nvnet/nvnet.c b/hw/xbox/mcpx/nvnet/nvnet.c index a7434c747c..ce58db2a64 100644 --- a/hw/xbox/mcpx/nvnet/nvnet.c +++ b/hw/xbox/mcpx/nvnet/nvnet.c @@ -287,12 +287,21 @@ static void reset_descriptor_ring_pointers(NvNetState *s) set_reg(s, NVNET_RX_RING_NEXT_DESC_PHYS_ADDR, base_desc_addr); } +static bool dma_enabled(NvNetState *s) +{ + return (get_reg(s, NVNET_TX_RX_CONTROL) & NVNET_TX_RX_CONTROL_BIT2) == 0; +} + static ssize_t dma_packet_to_guest(NvNetState *s, const uint8_t *buf, size_t size) { PCIDevice *d = PCI_DEVICE(s); ssize_t rval; + if (!dma_enabled(s)) { + return -1; + } + and_reg(s, NVNET_TX_RX_CONTROL, ~NVNET_TX_RX_CONTROL_IDLE); uint32_t base_desc_addr = get_reg(s, NVNET_RX_RING_PHYS_ADDR); @@ -357,6 +366,10 @@ static ssize_t dma_packet_from_guest(NvNetState *s) PCIDevice *d = PCI_DEVICE(s); bool packet_sent = false; + if (!dma_enabled(s)) { + return -1; + } + and_reg(s, NVNET_TX_RX_CONTROL, ~NVNET_TX_RX_CONTROL_IDLE); uint32_t base_desc_addr = get_reg(s, NVNET_TX_RING_PHYS_ADDR); @@ -435,8 +448,9 @@ static bool nvnet_can_receive(NetClientState *nc) NvNetState *s = qemu_get_nic_opaque(nc); bool link_up = s->phy_regs[MII_BMSR] & MII_BMSR_LINK_ST; + bool dma_en = dma_enabled(s); - return link_up; + return link_up && dma_en; } static bool is_packet_oversized(size_t size) @@ -746,11 +760,6 @@ static void nvnet_mmio_write(void *opaque, hwaddr addr, uint64_t val, dma_packet_from_guest(s); } - if (val & NVNET_TX_RX_CONTROL_BIT2) { - set_reg(s, NVNET_TX_RX_CONTROL, NVNET_TX_RX_CONTROL_IDLE); - break; - } - if (val & NVNET_TX_RX_CONTROL_RESET) { reset_descriptor_ring_pointers(s); s->tx_dma_buf_offset = 0;