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target/i386: replace NoSeg special with NoLoadEA 

This is a bit more generic, as it can be applied to MPX as well.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-05-09 16:56:26 +02:00
parent 4e2dc59cf9
commit c0df9563a3
3 changed files with 9 additions and 11 deletions
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12
target/i386/tcg/decode-new.c.inc
View File

@ -193,7 +193,7 @@
X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__) X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
#define cpuid(feat) .cpuid = X86_FEAT_##feat, #define cpuid(feat) .cpuid = X86_FEAT_##feat,
#define noseg .special = X86_SPECIAL_NoSeg, #define nolea .special = X86_SPECIAL_NoLoadEA,
#define xchg .special = X86_SPECIAL_Locked, #define xchg .special = X86_SPECIAL_Locked,
#define lock .special = X86_SPECIAL_HasLock, #define lock .special = X86_SPECIAL_HasLock,
#define mmx .special = X86_SPECIAL_MMX, #define mmx .special = X86_SPECIAL_MMX,
@ -1592,7 +1592,7 @@ static const X86OpEntry opcodes_root[256] = {
[0x8B] = X86_OP_ENTRYwr(MOV, G,v, E,v), [0x8B] = X86_OP_ENTRYwr(MOV, G,v, E,v),
/* Missing in Table A-2: memory destination is always 16-bit. */ /* Missing in Table A-2: memory destination is always 16-bit. */
[0x8C] = X86_OP_ENTRYwr(MOV, E,v, S,w, op0_Mw), [0x8C] = X86_OP_ENTRYwr(MOV, E,v, S,w, op0_Mw),
[0x8D] = X86_OP_ENTRYwr(LEA, G,v, M,v, noseg), [0x8D] = X86_OP_ENTRYwr(LEA, G,v, M,v, nolea),
[0x8E] = X86_OP_ENTRYwr(MOV, S,w, E,w), [0x8E] = X86_OP_ENTRYwr(MOV, S,w, E,w),
[0x8F] = X86_OP_GROUPw(group1A, E,v), [0x8F] = X86_OP_GROUPw(group1A, E,v),
@ -2524,11 +2524,6 @@ static void disas_insn(DisasContext *s, CPUState *cpu)
assert(decode.op[1].unit == X86_OP_INT); assert(decode.op[1].unit == X86_OP_INT);
break; break;
case X86_SPECIAL_NoSeg:
decode.mem.def_seg = -1;
s->override = -1;
break;
case X86_SPECIAL_Op0_Mw: case X86_SPECIAL_Op0_Mw:
assert(decode.op[0].unit == X86_OP_INT); assert(decode.op[0].unit == X86_OP_INT);
if (decode.op[0].has_ea) { if (decode.op[0].has_ea) {
@ -2585,7 +2580,8 @@ static void disas_insn(DisasContext *s, CPUState *cpu)
gen_helper_enter_mmx(tcg_env); gen_helper_enter_mmx(tcg_env);
} }
if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) { if (decode.e.special != X86_SPECIAL_NoLoadEA &&
(decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea)) {
gen_load_ea(s, &decode.mem, decode.e.vex_class == 12); gen_load_ea(s, &decode.mem, decode.e.vex_class == 12);
} }
if (s->prefix & PREFIX_LOCK) { if (s->prefix & PREFIX_LOCK) {

5
target/i386/tcg/decode-new.h
View File

@ -170,8 +170,9 @@ typedef enum X86InsnSpecial {
/* Always locked if it has a memory operand (XCHG) */ /* Always locked if it has a memory operand (XCHG) */
X86_SPECIAL_Locked, X86_SPECIAL_Locked,
/* Do not apply segment base to effective address */ /* Do not load effective address in s->A0 */
X86_SPECIAL_NoSeg, X86_SPECIAL_NoLoadEA,
/* /*
* Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits
* (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA * (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA

3
target/i386/tcg/emit.c.inc
View File

@ -1970,7 +1970,8 @@ static void gen_LDS(DisasContext *s, X86DecodedInsn *decode)
static void gen_LEA(DisasContext *s, X86DecodedInsn *decode) static void gen_LEA(DisasContext *s, X86DecodedInsn *decode)
{ {
tcg_gen_mov_tl(s->T0, s->A0); TCGv ea = gen_lea_modrm_1(s, decode->mem, false);
gen_lea_v_seg_dest(s, s->aflag, s->T0, ea, -1, -1);
} }
static void gen_LEAVE(DisasContext *s, X86DecodedInsn *decode) static void gen_LEAVE(DisasContext *s, X86DecodedInsn *decode)