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target/arm: Fix decode of FMOV (hp) vs MOVI 

The decode of FMOV (vector, immediate, half-precision) vs
invalid cases of MOVI are incorrect.

Fixes RISU mismatch for invalid insn 0x2f01fd31.

Fixes: 70b4e6a445 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-24 16:20:19 -07:00 committed by Peter Maydell
parent fe84877ed4
commit c0ca7ed049
1 changed files with 14 additions and 10 deletions
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24
target/arm/tcg/translate-a64.c
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@ -7904,27 +7904,31 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
bool is_q = extract32(insn, 30, 1);
uint64_t imm = 0;
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
/* Check for FMOV (vector, immediate) - half-precision */
if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) {
if (o2) {
if (cmode != 0xf || is_neg) {
unallocated_encoding(s);
return;
}
}
if (!fp_access_check(s)) {
return;
}
if (cmode == 15 && o2 && !is_neg) {
/* FMOV (vector, immediate) - half-precision */
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
imm = vfp_expand_imm(MO_16, abcdefgh);
/* now duplicate across the lanes */
imm = dup_const(MO_16, imm);
} else {
if (cmode == 0xf && is_neg && !is_q) {
unallocated_encoding(s);
return;
}
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
}
if (!fp_access_check(s)) {
return;
}
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
/* MOVI or MVNI, with MVNI negation handled above. */
tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,