ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/arm: Convert BR, BLR, RET to decodetree 

Convert the simple (non-pointer-auth) BR, BLR and RET insns
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-18-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-05-12 15:41:03 +01:00
parent 484df362dd
commit c0b5e3943b
2 changed files with 54 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
target/arm/tcg/a64.decode
View File

@ -19,6 +19,7 @@
# This file is processed by scripts/decodetree.py # This file is processed by scripts/decodetree.py
# #
&r rn
&ri rd imm &ri rd imm
&rri_sf rd rn imm sf &rri_sf rd rn imm sf
&i imm &i imm
@ -126,3 +127,7 @@ CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 B_cond 0101010 0 ................... 0 cond:4 imm=%imm19
BR 1101011 0000 11111 000000 rn:5 00000 &r
BLR 1101011 0001 11111 000000 rn:5 00000 &r
RET 1101011 0010 11111 000000 rn:5 00000 &r

55
target/arm/tcg/translate-a64.c
View File

@ -1388,6 +1388,53 @@ static bool trans_B_cond(DisasContext *s, arg_B_cond *a)
return true; return true;
} }
static void set_btype_for_br(DisasContext *s, int rn)
{
if (dc_isar_feature(aa64_bti, s)) {
/* BR to {x16,x17} or !guard -> 1, else 3. */
set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3);
}
}
static void set_btype_for_blr(DisasContext *s)
{
if (dc_isar_feature(aa64_bti, s)) {
/* BLR sets BTYPE to 2, regardless of source guarded page. */
set_btype(s, 2);
}
}
static bool trans_BR(DisasContext *s, arg_r *a)
{
gen_a64_set_pc(s, cpu_reg(s, a->rn));
set_btype_for_br(s, a->rn);
s->base.is_jmp = DISAS_JUMP;
return true;
}
static bool trans_BLR(DisasContext *s, arg_r *a)
{
TCGv_i64 dst = cpu_reg(s, a->rn);
TCGv_i64 lr = cpu_reg(s, 30);
if (dst == lr) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_mov_i64(tmp, dst);
dst = tmp;
}
gen_pc_plus_diff(s, lr, curr_insn_len(s));
gen_a64_set_pc(s, dst);
set_btype_for_blr(s);
s->base.is_jmp = DISAS_JUMP;
return true;
}
static bool trans_RET(DisasContext *s, arg_r *a)
{
gen_a64_set_pc(s, cpu_reg(s, a->rn));
s->base.is_jmp = DISAS_JUMP;
return true;
}
/* HINT instruction group, including various allocated HINTs */ /* HINT instruction group, including various allocated HINTs */
static void handle_hint(DisasContext *s, uint32_t insn, static void handle_hint(DisasContext *s, uint32_t insn,
unsigned int op1, unsigned int op2, unsigned int crm) unsigned int op1, unsigned int op2, unsigned int crm)
@ -2186,12 +2233,8 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
btype_mod = opc; btype_mod = opc;
switch (op3) { switch (op3) {
case 0: case 0:
/* BR, BLR, RET */ /* BR, BLR, RET : handled in decodetree */
if (op4 != 0) { goto do_unallocated;
goto do_unallocated;
}
dst = cpu_reg(s, rn);
break;
case 2: case 2:
case 3: case 3: