mirror of https://github.com/xemu-project/xemu.git
target/loongarch: Implement xvmax/xvmin
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-25-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
27f5485d95
commit
c09360faad
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@ -1856,6 +1856,40 @@ INSN_LASX(xvadda_h, vvv)
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INSN_LASX(xvadda_w, vvv)
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INSN_LASX(xvadda_d, vvv)
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INSN_LASX(xvmax_b, vvv)
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INSN_LASX(xvmax_h, vvv)
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INSN_LASX(xvmax_w, vvv)
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INSN_LASX(xvmax_d, vvv)
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INSN_LASX(xvmin_b, vvv)
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INSN_LASX(xvmin_h, vvv)
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INSN_LASX(xvmin_w, vvv)
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INSN_LASX(xvmin_d, vvv)
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INSN_LASX(xvmax_bu, vvv)
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INSN_LASX(xvmax_hu, vvv)
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INSN_LASX(xvmax_wu, vvv)
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INSN_LASX(xvmax_du, vvv)
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INSN_LASX(xvmin_bu, vvv)
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INSN_LASX(xvmin_hu, vvv)
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INSN_LASX(xvmin_wu, vvv)
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INSN_LASX(xvmin_du, vvv)
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INSN_LASX(xvmaxi_b, vv_i)
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INSN_LASX(xvmaxi_h, vv_i)
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INSN_LASX(xvmaxi_w, vv_i)
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INSN_LASX(xvmaxi_d, vv_i)
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INSN_LASX(xvmini_b, vv_i)
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INSN_LASX(xvmini_h, vv_i)
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INSN_LASX(xvmini_w, vv_i)
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INSN_LASX(xvmini_d, vv_i)
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INSN_LASX(xvmaxi_bu, vv_i)
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INSN_LASX(xvmaxi_hu, vv_i)
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INSN_LASX(xvmaxi_wu, vv_i)
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INSN_LASX(xvmaxi_du, vv_i)
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INSN_LASX(xvmini_bu, vv_i)
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INSN_LASX(xvmini_hu, vv_i)
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INSN_LASX(xvmini_wu, vv_i)
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INSN_LASX(xvmini_du, vv_i)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -1685,6 +1685,14 @@ TRANS(vmax_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umax)
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TRANS(vmax_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umax)
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TRANS(vmax_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umax)
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TRANS(vmax_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umax)
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TRANS(xvmax_b, LASX, gvec_xxx, MO_8, tcg_gen_gvec_smax)
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TRANS(xvmax_h, LASX, gvec_xxx, MO_16, tcg_gen_gvec_smax)
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TRANS(xvmax_w, LASX, gvec_xxx, MO_32, tcg_gen_gvec_smax)
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TRANS(xvmax_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_smax)
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TRANS(xvmax_bu, LASX, gvec_xxx, MO_8, tcg_gen_gvec_umax)
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TRANS(xvmax_hu, LASX, gvec_xxx, MO_16, tcg_gen_gvec_umax)
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TRANS(xvmax_wu, LASX, gvec_xxx, MO_32, tcg_gen_gvec_umax)
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TRANS(xvmax_du, LASX, gvec_xxx, MO_64, tcg_gen_gvec_umax)
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TRANS(vmin_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smin)
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TRANS(vmin_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smin)
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@ -1694,6 +1702,14 @@ TRANS(vmin_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umin)
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TRANS(vmin_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umin)
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TRANS(vmin_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umin)
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TRANS(vmin_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umin)
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TRANS(xvmin_b, LASX, gvec_xxx, MO_8, tcg_gen_gvec_smin)
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TRANS(xvmin_h, LASX, gvec_xxx, MO_16, tcg_gen_gvec_smin)
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TRANS(xvmin_w, LASX, gvec_xxx, MO_32, tcg_gen_gvec_smin)
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TRANS(xvmin_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_smin)
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TRANS(xvmin_bu, LASX, gvec_xxx, MO_8, tcg_gen_gvec_umin)
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TRANS(xvmin_hu, LASX, gvec_xxx, MO_16, tcg_gen_gvec_umin)
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TRANS(xvmin_wu, LASX, gvec_xxx, MO_32, tcg_gen_gvec_umin)
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TRANS(xvmin_du, LASX, gvec_xxx, MO_64, tcg_gen_gvec_umin)
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static void gen_vmini_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
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{
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@ -1795,6 +1811,14 @@ TRANS(vmini_bu, LSX, gvec_vv_i, MO_8, do_vmini_u)
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TRANS(vmini_hu, LSX, gvec_vv_i, MO_16, do_vmini_u)
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TRANS(vmini_wu, LSX, gvec_vv_i, MO_32, do_vmini_u)
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TRANS(vmini_du, LSX, gvec_vv_i, MO_64, do_vmini_u)
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TRANS(xvmini_b, LASX, gvec_xx_i, MO_8, do_vmini_s)
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TRANS(xvmini_h, LASX, gvec_xx_i, MO_16, do_vmini_s)
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TRANS(xvmini_w, LASX, gvec_xx_i, MO_32, do_vmini_s)
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TRANS(xvmini_d, LASX, gvec_xx_i, MO_64, do_vmini_s)
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TRANS(xvmini_bu, LASX, gvec_xx_i, MO_8, do_vmini_u)
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TRANS(xvmini_hu, LASX, gvec_xx_i, MO_16, do_vmini_u)
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TRANS(xvmini_wu, LASX, gvec_xx_i, MO_32, do_vmini_u)
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TRANS(xvmini_du, LASX, gvec_xx_i, MO_64, do_vmini_u)
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static void do_vmaxi_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
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int64_t imm, uint32_t oprsz, uint32_t maxsz)
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@ -1876,6 +1900,14 @@ TRANS(vmaxi_bu, LSX, gvec_vv_i, MO_8, do_vmaxi_u)
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TRANS(vmaxi_hu, LSX, gvec_vv_i, MO_16, do_vmaxi_u)
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TRANS(vmaxi_wu, LSX, gvec_vv_i, MO_32, do_vmaxi_u)
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TRANS(vmaxi_du, LSX, gvec_vv_i, MO_64, do_vmaxi_u)
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TRANS(xvmaxi_b, LASX, gvec_xx_i, MO_8, do_vmaxi_s)
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TRANS(xvmaxi_h, LASX, gvec_xx_i, MO_16, do_vmaxi_s)
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TRANS(xvmaxi_w, LASX, gvec_xx_i, MO_32, do_vmaxi_s)
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TRANS(xvmaxi_d, LASX, gvec_xx_i, MO_64, do_vmaxi_s)
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TRANS(xvmaxi_bu, LASX, gvec_xx_i, MO_8, do_vmaxi_u)
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TRANS(xvmaxi_hu, LASX, gvec_xx_i, MO_16, do_vmaxi_u)
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TRANS(xvmaxi_wu, LASX, gvec_xx_i, MO_32, do_vmaxi_u)
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TRANS(xvmaxi_du, LASX, gvec_xx_i, MO_64, do_vmaxi_u)
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TRANS(vmul_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_mul)
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TRANS(vmul_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_mul)
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@ -1437,6 +1437,42 @@ xvadda_h 0111 01000101 11001 ..... ..... ..... @vvv
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xvadda_w 0111 01000101 11010 ..... ..... ..... @vvv
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xvadda_d 0111 01000101 11011 ..... ..... ..... @vvv
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xvmax_b 0111 01000111 00000 ..... ..... ..... @vvv
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xvmax_h 0111 01000111 00001 ..... ..... ..... @vvv
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xvmax_w 0111 01000111 00010 ..... ..... ..... @vvv
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xvmax_d 0111 01000111 00011 ..... ..... ..... @vvv
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xvmax_bu 0111 01000111 01000 ..... ..... ..... @vvv
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xvmax_hu 0111 01000111 01001 ..... ..... ..... @vvv
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xvmax_wu 0111 01000111 01010 ..... ..... ..... @vvv
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xvmax_du 0111 01000111 01011 ..... ..... ..... @vvv
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xvmaxi_b 0111 01101001 00000 ..... ..... ..... @vv_i5
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xvmaxi_h 0111 01101001 00001 ..... ..... ..... @vv_i5
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xvmaxi_w 0111 01101001 00010 ..... ..... ..... @vv_i5
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xvmaxi_d 0111 01101001 00011 ..... ..... ..... @vv_i5
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xvmaxi_bu 0111 01101001 01000 ..... ..... ..... @vv_ui5
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xvmaxi_hu 0111 01101001 01001 ..... ..... ..... @vv_ui5
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xvmaxi_wu 0111 01101001 01010 ..... ..... ..... @vv_ui5
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xvmaxi_du 0111 01101001 01011 ..... ..... ..... @vv_ui5
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xvmin_b 0111 01000111 00100 ..... ..... ..... @vvv
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xvmin_h 0111 01000111 00101 ..... ..... ..... @vvv
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xvmin_w 0111 01000111 00110 ..... ..... ..... @vvv
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xvmin_d 0111 01000111 00111 ..... ..... ..... @vvv
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xvmin_bu 0111 01000111 01100 ..... ..... ..... @vvv
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xvmin_hu 0111 01000111 01101 ..... ..... ..... @vvv
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xvmin_wu 0111 01000111 01110 ..... ..... ..... @vvv
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xvmin_du 0111 01000111 01111 ..... ..... ..... @vvv
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xvmini_b 0111 01101001 00100 ..... ..... ..... @vv_i5
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xvmini_h 0111 01101001 00101 ..... ..... ..... @vv_i5
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xvmini_w 0111 01101001 00110 ..... ..... ..... @vv_i5
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xvmini_d 0111 01101001 00111 ..... ..... ..... @vv_i5
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xvmini_bu 0111 01101001 01100 ..... ..... ..... @vv_ui5
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xvmini_hu 0111 01101001 01101 ..... ..... ..... @vv_ui5
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xvmini_wu 0111 01101001 01110 ..... ..... ..... @vv_ui5
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xvmini_du 0111 01101001 01111 ..... ..... ..... @vv_ui5
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -416,17 +416,18 @@ DO_VADDA(vadda_d, 64, D)
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#define DO_MIN(a, b) (a < b ? a : b)
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#define DO_MAX(a, b) (a > b ? a : b)
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#define VMINMAXI(NAME, BIT, E, DO_OP) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t v) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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typedef __typeof(Vd->E(0)) TD; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E(i) = DO_OP(Vj->E(i), (TD)imm); \
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} \
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#define VMINMAXI(NAME, BIT, E, DO_OP) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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typedef __typeof(Vd->E(0)) TD; \
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int oprsz = simd_oprsz(desc); \
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\
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for (i = 0; i < oprsz / (BIT / 8); i++) { \
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Vd->E(i) = DO_OP(Vj->E(i), (TD)imm); \
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} \
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}
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VMINMAXI(vmini_b, 8, B, DO_MIN)
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