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riscv: Change type of valid_vm_1_10_[32|64] to bool 

This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230303131252.892893-3-alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Alexandre Ghiti 2023-03-03 14:12:49 +01:00 committed by Palmer Dabbelt
parent c01756a76e
commit bf1a6abec4
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 11 additions and 10 deletions
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21
target/riscv/csr.c
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@ -1141,16 +1141,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP; static const target_ulong vsip_writable_mask = MIP_VSSIP;
static const char valid_vm_1_10_32[16] = { static const bool valid_vm_1_10_32[16] = {
[VM_1_10_MBARE] = 1, [VM_1_10_MBARE] = true,
[VM_1_10_SV32] = 1 [VM_1_10_SV32] = true
}; };
static const char valid_vm_1_10_64[16] = { static const bool valid_vm_1_10_64[16] = {
[VM_1_10_MBARE] = 1, [VM_1_10_MBARE] = true,
[VM_1_10_SV39] = 1, [VM_1_10_SV39] = true,
[VM_1_10_SV48] = 1, [VM_1_10_SV48] = true,
[VM_1_10_SV57] = 1 [VM_1_10_SV57] = true
}; };
/* Machine Information Registers */ /* Machine Information Registers */
@ -1230,7 +1230,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static int validate_vm(CPURISCVState *env, target_ulong vm) static bool validate_vm(CPURISCVState *env, target_ulong vm)
{ {
if (riscv_cpu_mxl(env) == MXL_RV32) { if (riscv_cpu_mxl(env) == MXL_RV32) {
return valid_vm_1_10_32[vm & 0xf]; return valid_vm_1_10_32[vm & 0xf];
@ -2669,7 +2669,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
static RISCVException write_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
target_ulong vm, mask; target_ulong mask;
bool vm;
if (!riscv_cpu_cfg(env)->mmu) { if (!riscv_cpu_cfg(env)->mmu) {
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;