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target/i386: Assert !ADDSEG for x86_64 user-only 

LMA disables traditional segmentation, exposing a flat address space.
This means that ADDSEG is off.

Since we're adding an accessor macro, pull the value directly out
of flags otherwise.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210514151342.384376-15-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-14 10:13:06 -05:00
parent 73e90dc458
commit beedb93c04
1 changed files with 6 additions and 5 deletions
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11
target/i386/tcg/translate.c
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@ -108,7 +108,6 @@ typedef struct DisasContext {
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
bool x86_64_hregs; bool x86_64_hregs;
#endif #endif
int addseg; /* non zero if either DS/ES/SS have a non zero base */
int f_st; /* currently unused */ int f_st; /* currently unused */
int tf; /* TF cpu flag */ int tf; /* TF cpu flag */
int jmp_opt; /* use direct block chaining for direct jumps */ int jmp_opt; /* use direct block chaining for direct jumps */
@ -156,10 +155,12 @@ typedef struct DisasContext {
#define VM86(S) false #define VM86(S) false
#define CODE32(S) true #define CODE32(S) true
#define SS32(S) true #define SS32(S) true
#define ADDSEG(S) false
#else #else
#define VM86(S) (((S)->flags & HF_VM_MASK) != 0) #define VM86(S) (((S)->flags & HF_VM_MASK) != 0)
#define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0)
#define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) != 0)
#define ADDSEG(S) (((S)->flags & HF_ADDSEG_MASK) != 0)
#endif #endif
#if !defined(TARGET_X86_64) #if !defined(TARGET_X86_64)
#define CODE64(S) false #define CODE64(S) false
@ -492,7 +493,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0,
#endif #endif
case MO_32: case MO_32:
/* 32 bit address */ /* 32 bit address */
if (ovr_seg < 0 && s->addseg) { if (ovr_seg < 0 && ADDSEG(s)) {
ovr_seg = def_seg; ovr_seg = def_seg;
} }
if (ovr_seg < 0) { if (ovr_seg < 0) {
@ -505,7 +506,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0,
tcg_gen_ext16u_tl(s->A0, a0); tcg_gen_ext16u_tl(s->A0, a0);
a0 = s->A0; a0 = s->A0;
if (ovr_seg < 0) { if (ovr_seg < 0) {
if (s->addseg) { if (ADDSEG(s)) {
ovr_seg = def_seg; ovr_seg = def_seg;
} else { } else {
return; return;
@ -2429,7 +2430,7 @@ static void gen_push_v(DisasContext *s, TCGv val)
tcg_gen_subi_tl(s->A0, cpu_regs[R_ESP], size); tcg_gen_subi_tl(s->A0, cpu_regs[R_ESP], size);
if (!CODE64(s)) { if (!CODE64(s)) {
if (s->addseg) { if (ADDSEG(s)) {
new_esp = s->tmp4; new_esp = s->tmp4;
tcg_gen_mov_tl(new_esp, s->A0); tcg_gen_mov_tl(new_esp, s->A0);
} }
@ -8506,8 +8507,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0));
g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0));
g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0));
g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0));
dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
dc->f_st = 0; dc->f_st = 0;
dc->tf = (flags >> TF_SHIFT) & 1; dc->tf = (flags >> TF_SHIFT) & 1;
dc->cc_op = CC_OP_DYNAMIC; dc->cc_op = CC_OP_DYNAMIC;