ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/arm: Convert load (pointer auth) insns to decodetree 

Convert the instructions in the load/store register (pointer
authentication) group ot decodetree: LDRAA, LDRAB.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-06-19 11:20:23 +01:00
parent 54a9ab74ed
commit be23a049ec
2 changed files with 23 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
target/arm/tcg/a64.decode
View File

@ -457,3 +457,10 @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic
SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic
LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
# Load/store register (pointer authentication)
# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
%ldra_imm 22:s1 12:9 !function=times_2
LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm

83
target/arm/tcg/translate-a64.c
View File

@ -3324,43 +3324,23 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a)
return true;
}
/*
* PAC memory operations
*
* 31 30 27 26 24 22 21 12 11 10 5 0
* +------+-------+---+-----+-----+---+--------+---+---+----+-----+
* | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
* +------+-------+---+-----+-----+---+--------+---+---+----+-----+
*
* Rt: the result register
* Rn: base address or SP
* V: vector flag (always 0 as of v8.3)
* M: clear for key DA, set for key DB
* W: pre-indexing flag
* S: sign for imm9.
*/
static void disas_ldst_pac(DisasContext *s, uint32_t insn,
int size, int rt, bool is_vector)
static bool trans_LDRA(DisasContext *s, arg_LDRA *a)
{
int rn = extract32(insn, 5, 5);
bool is_wback = extract32(insn, 11, 1);
bool use_key_a = !extract32(insn, 23, 1);
int offset;
TCGv_i64 clean_addr, dirty_addr, tcg_rt;
MemOp memop;
if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
unallocated_encoding(s);
return;
/* Load with pointer authentication */
if (!dc_isar_feature(aa64_pauth, s)) {
return false;
}
if (rn == 31) {
if (a->rn == 31) {
gen_check_sp_alignment(s);
}
dirty_addr = read_cpu_reg_sp(s, rn, 1);
dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
if (s->pauth_active) {
if (use_key_a) {
if (!a->m) {
gen_helper_autda(dirty_addr, cpu_env, dirty_addr,
tcg_constant_i64(0));
} else {
@ -3369,25 +3349,23 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
}
}
/* Form the 10-bit signed, scaled offset. */
offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9);
offset = sextract32(offset << size, 0, 10 + size);
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm);
memop = finalize_memop(s, size);
memop = finalize_memop(s, MO_64);
/* Note that "clean" and "dirty" here refer to TBI not PAC. */
clean_addr = gen_mte_check1(s, dirty_addr, false,
is_wback || rn != 31, memop);
a->w || a->rn != 31, memop);
tcg_rt = cpu_reg(s, rt);
tcg_rt = cpu_reg(s, a->rt);
do_gpr_ld(s, tcg_rt, clean_addr, memop,
/* extend */ false, /* iss_valid */ !is_wback,
/* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
/* extend */ false, /* iss_valid */ !a->w,
/* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false);
if (is_wback) {
tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr);
if (a->w) {
tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr);
}
return true;
}
/*
@ -3474,31 +3452,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
}
}
/* Load/store register (all forms) */
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
{
int rt = extract32(insn, 0, 5);
bool is_vector = extract32(insn, 26, 1);
int size = extract32(insn, 30, 2);
switch (extract32(insn, 24, 2)) {
case 0:
if (extract32(insn, 21, 1) == 0) {
break;
}
switch (extract32(insn, 10, 2)) {
case 0:
case 2:
break;
default:
disas_ldst_pac(s, insn, size, rt, is_vector);
return;
}
break;
}
unallocated_encoding(s);
}
/* AdvSIMD load/store multiple structures
*
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
@ -4016,10 +3969,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
static void disas_ldst(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 24, 6)) {
case 0x38: case 0x39:
case 0x3c: case 0x3d: /* Load/store register (all forms) */
disas_ldst_reg(s, insn);
break;
case 0x0c: /* AdvSIMD load/store multiple structures */
disas_ldst_multiple_struct(s, insn);
break;