mirror of https://github.com/xemu-project/xemu.git
MIPS patches 2015-08-13
Changes: * mips32r5-generic CPU updated and renamed to P5600 * improvements in LWL/LDL, logging and fulong2e -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJVzMGTAAoJEFIRjjwLKdprClUH/2col9J1MIoYm+8Ac8Q5hBd5 Bpg1HvWql8ecx29z9bhDNkitXATaMkwho05aEl0xkYzjhKMvjs2ayTuko35ryOY6 KRSONpndvfJLDCaxdrQcvKG9DXmhSPIy2TZLv0Jpl0dfhPXm0LPxv3WQ/s8YZJa7 e2bGmUNLyloySMEmq7T55U4FCB/eyzzLBreCR4miOxU+KBKSAQyZBB9dcCj52sCM qA8OtaQZdKXUYvqwd+mRpCUjvqhrfFmMSV/A0VclXHCxb9lX63HY1c7X6bHzNyoP YWwCJLadQsYMUl4ajF+phUrWu6mjRgpcpQKSYiX8+u2gdcbVY6TeyzjYfsczLf8= =Owqn -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150813' into staging MIPS patches 2015-08-13 Changes: * mips32r5-generic CPU updated and renamed to P5600 * improvements in LWL/LDL, logging and fulong2e # gpg: Signature made Thu 13 Aug 2015 17:10:59 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150813: target-mips: Use CPU_LOG_INT for logging related to interrupts hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses target-mips: simplify LWL/LDL mask generation target-mips: update mips32r5-generic into P5600 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
be1f13ac9d
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@ -355,6 +355,10 @@ static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
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uint32_t val;
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PCIBonitoState *s = opaque;
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if (addr >= sizeof(s->bonldma)) {
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return 0;
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}
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val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
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return val;
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@ -365,6 +369,10 @@ static void bonito_ldma_writel(void *opaque, hwaddr addr,
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{
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PCIBonitoState *s = opaque;
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if (addr >= sizeof(s->bonldma)) {
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return;
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}
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((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
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}
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@ -384,6 +392,10 @@ static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
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uint32_t val;
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PCIBonitoState *s = opaque;
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if (addr >= sizeof(s->boncop)) {
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return 0;
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}
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val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
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return val;
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@ -394,6 +406,10 @@ static void bonito_cop_writel(void *opaque, hwaddr addr,
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{
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PCIBonitoState *s = opaque;
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if (addr >= sizeof(s->boncop)) {
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return;
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}
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((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
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}
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@ -395,7 +395,7 @@ struct CPUMIPSState {
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#define CP0C0_K23 28
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#define CP0C0_KU 25
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#define CP0C0_MDU 20
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#define CP0C0_MM 17
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#define CP0C0_MM 18
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#define CP0C0_BM 16
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#define CP0C0_BE 15
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#define CP0C0_AT 13
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@ -127,10 +127,6 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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/* effective address (modified for KVM T&E kernel segments) */
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target_ulong address = real_address;
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#if 0
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qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
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#endif
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#define USEG_LIMIT 0x7FFFFFFFUL
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#define KSEG0_BASE 0x80000000UL
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#define KSEG1_BASE 0xA0000000UL
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@ -227,11 +223,6 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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ret = TLBRET_BADADDR;
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}
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}
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#if 0
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qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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#endif
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return ret;
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}
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#endif
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@ -487,14 +478,16 @@ void mips_cpu_do_interrupt(CPUState *cs)
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int cause = -1;
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const char *name;
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if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
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if (qemu_loglevel_mask(CPU_LOG_INT)
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&& cs->exception_index != EXCP_EXT_INTERRUPT) {
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if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
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name = "unknown";
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} else {
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name = excp_names[cs->exception_index];
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}
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qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
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qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
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" %s exception\n",
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__func__, env->active_tc.PC, env->CP0_EPC, name);
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}
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if (cs->exception_index == EXCP_EXT_INTERRUPT &&
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@ -747,16 +740,15 @@ void mips_cpu_do_interrupt(CPUState *cs)
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
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break;
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default:
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qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
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printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
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exit(1);
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abort();
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}
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if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
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if (qemu_loglevel_mask(CPU_LOG_INT)
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&& cs->exception_index != EXCP_EXT_INTERRUPT) {
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qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
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" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
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__func__, env->active_tc.PC, env->CP0_EPC, cause,
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env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
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env->CP0_DEPC);
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" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
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__func__, env->active_tc.PC, env->CP0_EPC, cause,
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env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
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env->CP0_DEPC);
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}
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#endif
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cs->exception_index = EXCP_NONE;
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@ -38,7 +38,8 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
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CPUState *cs = CPU(mips_env_get_cpu(env));
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if (exception < EXCP_SC) {
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qemu_log("%s: %d %d\n", __func__, exception, error_code);
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qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
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__func__, exception, error_code);
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}
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cs->exception_index = exception;
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env->error_code = error_code;
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@ -2153,11 +2153,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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tcg_gen_andi_tl(t0, t0, ~7);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_shl_tl(t0, t0, t1);
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tcg_gen_xori_tl(t1, t1, 63);
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t2 = tcg_const_tl(0x7fffffffffffffffull);
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tcg_gen_shr_tl(t2, t2, t1);
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t2 = tcg_const_tl(-1);
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tcg_gen_shl_tl(t2, t2, t1);
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gen_load_gpr(t1, rt);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_gen_andc_tl(t1, t1, t2);
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tcg_temp_free(t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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@ -2246,11 +2245,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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tcg_gen_andi_tl(t0, t0, ~3);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_shl_tl(t0, t0, t1);
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tcg_gen_xori_tl(t1, t1, 31);
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t2 = tcg_const_tl(0x7fffffffull);
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tcg_gen_shr_tl(t2, t2, t1);
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t2 = tcg_const_tl(-1);
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tcg_gen_shl_tl(t2, t2, t1);
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gen_load_gpr(t1, rt);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_gen_andc_tl(t1, t1, t2);
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tcg_temp_free(t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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@ -389,39 +389,44 @@ static const mips_def_t mips_defs[] =
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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/* A generic CPU providing MIPS32 Release 5 features.
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FIXME: Eventually this should be replaced by a real CPU model. */
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.name = "mips32r5-generic",
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.CP0_PRid = 0x00019700,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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/* FIXME:
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* Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
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* Config4: MMUExtDef
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* Config5: EVA, MRP
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* FIR(FCR0): Has2008
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* */
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.name = "P5600",
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.CP0_PRid = 0x0001A800,
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.CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
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(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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(1 << CP0C1_PC) | (1 << CP0C1_FP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
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(1 << CP0C3_LPA),
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.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
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(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
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(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
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.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
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(0x1c << CP0C4_KScrExist),
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.CP0_Config4_rw_bitmask = 0,
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB) |
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(1 << CP0C5_MVH),
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.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
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(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
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(1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
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(0 << CP0C5_NFExists),
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
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.CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
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(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
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(1 << CP0C5_FRE) | (1 << CP0C5_UFR),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.CP0_LLAddr_shift = 0,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x3778FF1F,
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.CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
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.CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x93 << FCR0_PRID),
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.CP0_Status_rw_bitmask = 0x3C68FF1F,
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.CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
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(1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
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.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_F64) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x03 << FCR0_PRID),
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.SEGBITS = 32,
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.PABITS = 40,
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.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
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.insn_flags = CPU_MIPS32R5 | ASE_MSA,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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