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target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk 

As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the
initial PA space used for stage 2 table walks is assigned based on the SW
and NSW bits of the VSTCR and VTCR registers.
This was already implemented for the recursive stage 2 page table walks
in S1_ptw_translate(), but was missing for the final stage 2 walk.

Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220327093427.1548629-3-idan.horowitz@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Idan Horowitz 2022-04-01 15:35:49 +01:00 committed by Peter Maydell
parent d3b2d19111
commit bcd7a8cf38
1 changed files with 10 additions and 0 deletions
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10
target/arm/helper.c
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@ -12657,6 +12657,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
return ret;
}
if (arm_is_secure_below_el3(env)) {
if (attrs->secure) {
attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
} else {
attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
}
} else {
assert(!attrs->secure);
}
s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;