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hw/pcie: fix the generic pcie root port to support migration 

Add msix state to pcie-root-ports's vmstate
in order to support migration.

Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Marcel Apfelbaum 2017-06-07 15:43:59 +03:00 committed by Michael S. Tsirkin
parent 20fdef58a0
commit bc277a52fb
2 changed files with 29 additions and 0 deletions
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25
hw/pci-bridge/gen_pcie_root_port.c
View File

@ -20,6 +20,14 @@
#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1
typedef struct GenPCIERootPort {
/*< private >*/
PCIESlot parent_obj;
/*< public >*/
bool migrate_msix;
} GenPCIERootPort;
static uint8_t gen_rp_aer_vector(const PCIDevice *d) static uint8_t gen_rp_aer_vector(const PCIDevice *d)
{ {
return 0; return 0;
@ -45,6 +53,13 @@ static void gen_rp_interrupts_uninit(PCIDevice *d)
msix_uninit_exclusive_bar(d); msix_uninit_exclusive_bar(d);
} }
static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
{
GenPCIERootPort *rp = opaque;
return rp->migrate_msix;
}
static const VMStateDescription vmstate_rp_dev = { static const VMStateDescription vmstate_rp_dev = {
.name = "pcie-root-port", .name = "pcie-root-port",
.version_id = 1, .version_id = 1,
@ -54,10 +69,18 @@ static const VMStateDescription vmstate_rp_dev = {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
GenPCIERootPort,
gen_rp_test_migrate_msix),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
static Property gen_rp_props[] = {
DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true),
DEFINE_PROP_END_OF_LIST()
};
static void gen_rp_dev_class_init(ObjectClass *klass, void *data) static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
@ -68,6 +91,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP; k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
dc->desc = "PCI Express Root Port"; dc->desc = "PCI Express Root Port";
dc->vmsd = &vmstate_rp_dev; dc->vmsd = &vmstate_rp_dev;
dc->props = gen_rp_props;
rpc->aer_vector = gen_rp_aer_vector; rpc->aer_vector = gen_rp_aer_vector;
rpc->interrupts_init = gen_rp_interrupts_init; rpc->interrupts_init = gen_rp_interrupts_init;
rpc->interrupts_uninit = gen_rp_interrupts_uninit; rpc->interrupts_uninit = gen_rp_interrupts_uninit;
@ -77,6 +101,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
static const TypeInfo gen_rp_dev_info = { static const TypeInfo gen_rp_dev_info = {
.name = TYPE_GEN_PCIE_ROOT_PORT, .name = TYPE_GEN_PCIE_ROOT_PORT,
.parent = TYPE_PCIE_ROOT_PORT, .parent = TYPE_PCIE_ROOT_PORT,
.instance_size = sizeof(GenPCIERootPort),
.class_init = gen_rp_dev_class_init, .class_init = gen_rp_dev_class_init,
}; };

4
include/hw/compat.h
View File

@ -14,6 +14,10 @@
.driver = "virtio-net-device",\ .driver = "virtio-net-device",\
.property = "x-mtu-bypass-backend",\ .property = "x-mtu-bypass-backend",\
.value = "off",\ .value = "off",\
},{\
.driver = "pcie-root-port",\
.property = "x-migrate-msix",\
.value = "false",\
}, },
#define HW_COMPAT_2_8 \ #define HW_COMPAT_2_8 \