mirror of https://github.com/xemu-project/xemu.git
i2c: Don't check return value from i2c_recv()
i2c_recv() cannot fail, so there is no need to check the return value. It also returns unt8_t, so comparing with < 0 is not meaningful. Fix up various I2C controllers to remove the unneeded code. Signed-off-by: Corey Minyard <cminyard@mvista.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
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@ -189,16 +189,11 @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
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static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
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{
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int ret;
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uint8_t ret;
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aspeed_i2c_set_state(bus, I2CD_MRXD);
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ret = i2c_recv(bus->bus);
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if (ret < 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
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ret = 0xff;
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} else {
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bus->intr_status |= I2CD_INTR_RX_DONE;
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}
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bus->intr_status |= I2CD_INTR_RX_DONE;
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bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
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if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
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i2c_nack(bus->bus);
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@ -106,16 +106,10 @@ static inline void exynos4210_i2c_raise_interrupt(Exynos4210I2CState *s)
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static void exynos4210_i2c_data_receive(void *opaque)
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{
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Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
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int ret;
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s->i2cstat &= ~I2CSTAT_LAST_BIT;
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s->scl_free = false;
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ret = i2c_recv(s->bus);
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if (ret < 0 && (s->i2ccon & I2CCON_ACK_GEN)) {
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s->i2cstat |= I2CSTAT_LAST_BIT; /* Data is not acknowledged */
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} else {
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s->i2cds = ret;
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}
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s->i2cds = i2c_recv(s->bus);
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exynos4210_i2c_raise_interrupt(s);
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}
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@ -120,7 +120,7 @@ static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
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value = s->i2dr_read;
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if (imx_i2c_is_master(s)) {
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int ret = 0xff;
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uint8_t ret = 0xff;
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if (s->address == ADDR_RESET) {
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/* something is wrong as the address is not set */
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@ -133,15 +133,7 @@ static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
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} else {
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/* get the next byte */
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ret = i2c_recv(s->bus);
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if (ret >= 0) {
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imx_i2c_raise_interrupt(s);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
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"for device 0x%02x\n", TYPE_IMX_I2C,
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__func__, s->address);
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ret = 0xff;
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}
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imx_i2c_raise_interrupt(s);
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}
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s->i2dr_read = ret;
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