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hw/ppc: SPI controller wiring to P10 chip 

In this commit, create SPI controller on p10 chip and connect cs irq.

The QOM tree of pnv-spi and seeprom are.
/machine (powernv10-machine)
  /chip[0] (power10_v2.0-pnv-chip)
    /pib_spic[2] (pnv-spi)
      /pnv-spi-bus.2 (SSI)
      /xscom-spi[0] (memory-region)

/machine (powernv10-machine)
  /peripheral-anon (container)
    /device[0] (25csm04)
      /WP#[0] (irq)
      /ssi-gpio-cs[0] (irq)

(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"

Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Chalapathi V 2024-06-26 04:05:27 -05:00 committed by Nicholas Piggin
parent 8d970f4162
commit bb44dc4862
3 changed files with 31 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
hw/ppc/pnv.c
View File

@ -1962,6 +1962,11 @@ static void pnv_chip_power10_instance_init(Object *obj)
for (i = 0; i < pcc->i2c_num_engines; i++) {
object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
}
for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i],
TYPE_PNV_SPI);
}
}
static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
@ -2185,7 +2190,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&chip10->psi),
PSIHB9_IRQ_SBE_I2C));
}
/* PIB SPI Controller */
for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num",
i, &error_fatal);
/* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */
object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len",
(i == 2) ? 1 : 4, &error_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
(&chip10->pib_spic[i])), errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE +
i * PNV10_XSCOM_PIB_SPIC_SIZE,
&chip10->pib_spic[i].xscom_spic_regs);
}
}
static void pnv_rainier_i2c_init(PnvMachineState *pnv)

8
hw/ssi/pnv_spi.c
View File

@ -1051,9 +1051,17 @@ static void operation_sequencer(PnvSpi *s)
static void do_reset(DeviceState *dev)
{
PnvSpi *s = PNV_SPI(dev);
DeviceState *ssi_dev;
trace_pnv_spi_reset();
/* Connect cs irq */
ssi_dev = ssi_get_cs(s->ssi_bus, 0);
if (ssi_dev) {
qemu_irq cs_line = qdev_get_gpio_in_named(ssi_dev, SSI_GPIO_CS, 0);
qdev_connect_gpio_out_named(DEVICE(s), "cs", 0, cs_line);
}
/* Reset all N1 and N2 counters, and other constants */
s->N2_bits = 0;
s->N2_bytes = 0;

3
include/hw/ppc/pnv_chip.h
View File

@ -7,6 +7,7 @@
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_homer.h"
#include "hw/ppc/pnv_n1_chiplet.h"
#include "hw/ssi/pnv_spi.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_psi.h"
@ -123,6 +124,8 @@ struct Pnv10Chip {
PnvSBE sbe;
PnvHomer homer;
PnvN1Chiplet n1_chiplet;
#define PNV10_CHIP_MAX_PIB_SPIC 6
PnvSpi pib_spic[PNV10_CHIP_MAX_PIB_SPIC];
uint32_t nr_quads;
PnvQuad *quads;