mirror of https://github.com/xemu-project/xemu.git
hw/ppc: SPI controller wiring to P10 chip
In this commit, create SPI controller on p10 chip and connect cs irq. The QOM tree of pnv-spi and seeprom are. /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[2] (pnv-spi) /pnv-spi-bus.2 (SSI) /xscom-spi[0] (memory-region) /machine (powernv10-machine) /peripheral-anon (container) /device[0] (25csm04) /WP#[0] (irq) /ssi-gpio-cs[0] (irq) (qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus" "/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2" Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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parent
8d970f4162
commit
bb44dc4862
21
hw/ppc/pnv.c
21
hw/ppc/pnv.c
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@ -1962,6 +1962,11 @@ static void pnv_chip_power10_instance_init(Object *obj)
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for (i = 0; i < pcc->i2c_num_engines; i++) {
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object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
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}
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for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
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object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i],
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TYPE_PNV_SPI);
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}
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}
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static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
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@ -2185,7 +2190,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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qdev_get_gpio_in(DEVICE(&chip10->psi),
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PSIHB9_IRQ_SBE_I2C));
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}
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/* PIB SPI Controller */
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for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
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object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num",
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i, &error_fatal);
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/* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */
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object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len",
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(i == 2) ? 1 : 4, &error_fatal);
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if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
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(&chip10->pib_spic[i])), errp)) {
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return;
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}
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE +
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i * PNV10_XSCOM_PIB_SPIC_SIZE,
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&chip10->pib_spic[i].xscom_spic_regs);
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}
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}
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static void pnv_rainier_i2c_init(PnvMachineState *pnv)
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@ -1051,9 +1051,17 @@ static void operation_sequencer(PnvSpi *s)
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static void do_reset(DeviceState *dev)
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{
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PnvSpi *s = PNV_SPI(dev);
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DeviceState *ssi_dev;
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trace_pnv_spi_reset();
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/* Connect cs irq */
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ssi_dev = ssi_get_cs(s->ssi_bus, 0);
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if (ssi_dev) {
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qemu_irq cs_line = qdev_get_gpio_in_named(ssi_dev, SSI_GPIO_CS, 0);
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qdev_connect_gpio_out_named(DEVICE(s), "cs", 0, cs_line);
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}
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/* Reset all N1 and N2 counters, and other constants */
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s->N2_bits = 0;
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s->N2_bytes = 0;
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@ -7,6 +7,7 @@
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#include "hw/ppc/pnv_core.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_n1_chiplet.h"
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#include "hw/ssi/pnv_spi.h"
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_psi.h"
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@ -123,6 +124,8 @@ struct Pnv10Chip {
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PnvSBE sbe;
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PnvHomer homer;
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PnvN1Chiplet n1_chiplet;
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#define PNV10_CHIP_MAX_PIB_SPIC 6
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PnvSpi pib_spic[PNV10_CHIP_MAX_PIB_SPIC];
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uint32_t nr_quads;
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PnvQuad *quads;
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