mirror of https://github.com/xemu-project/xemu.git
target/i386: add support for LAM in CPUID enumeration
Linear Address Masking (LAM) is a new Intel CPU feature, which allows software to use of the untranslated address bits for metadata. The bit definition: CPUID.(EAX=7,ECX=1):EAX[26] Add CPUID definition for LAM. Note LAM feature is not supported for TCG of target-i386, LAM CPIUD bit will not be added to TCG_7_1_EAX_FEATURES. More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)" https://cdrdv2.intel.com/v1/dl/getContent/671368 Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com> Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com> Tested-by: Xuelian Guo <xuelian.guo@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240112060042.19925-2-binbin.wu@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -969,7 +969,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"fsrc", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, "amx-fp16", NULL, "avx-ifma",
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NULL, NULL, NULL, NULL,
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NULL, NULL, "lam", NULL,
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NULL, NULL, NULL, NULL,
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},
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.cpuid = {
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@ -927,6 +927,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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/* Support for VPMADD52[H,L]UQ */
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#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
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/* Linear Address Masking */
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#define CPUID_7_1_EAX_LAM (1U << 26)
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/* Support for VPDPB[SU,UU,SS]D[,S] */
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#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
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