mirror of https://github.com/xemu-project/xemu.git
hw/arm/virt: Add gic-version option to virt machine
Add gic_version to VirtMachineState, set it to value of the option and pass it around where necessary. Instantiate devices and fdt nodes according to the choice. max_cpus for virt machine increased to 123 (calculated from redistributor space available in the memory map). GICv2 compatibility check happens inside arm_gic_common_realize(). ITS region is added to the memory map too, however currently it not used, just reserved. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Tested-by: Ashok kumar <ashoks@broadcom.com> [PMM: Added missing cpu_to_le* calls, thanks to Shannon Zhao] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Pavel Fedin
Peter Maydell
parent
a7bf30342e
commit
b92ad3949b
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@ -443,33 +443,43 @@ build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
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madt = acpi_data_push(table_data, sizeof *madt);
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for (i = 0; i < guest_info->smp_cpus; i++) {
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AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
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sizeof *gicc);
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gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
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gicc->length = sizeof(*gicc);
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gicc->base_address = memmap[VIRT_GIC_CPU].base;
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gicc->cpu_interface_number = i;
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gicc->arm_mpidr = i;
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gicc->uid = i;
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if (test_bit(i, cpuinfo->found_cpus)) {
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gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
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}
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}
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gicd = acpi_data_push(table_data, sizeof *gicd);
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gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
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gicd->length = sizeof(*gicd);
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gicd->base_address = memmap[VIRT_GIC_DIST].base;
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gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
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gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
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gic_msi->length = sizeof(*gic_msi);
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gic_msi->gic_msi_frame_id = 0;
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gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
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gic_msi->flags = cpu_to_le32(1);
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gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
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gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
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if (guest_info->gic_version == 3) {
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AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
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sizeof *gicr);
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gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
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gicr->length = sizeof(*gicr);
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gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
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gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
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} else {
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for (i = 0; i < guest_info->smp_cpus; i++) {
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AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
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sizeof *gicc);
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gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
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gicc->length = sizeof(*gicc);
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gicc->base_address = memmap[VIRT_GIC_CPU].base;
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gicc->cpu_interface_number = i;
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gicc->arm_mpidr = i;
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gicc->uid = i;
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if (test_bit(i, cpuinfo->found_cpus)) {
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gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
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}
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}
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gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
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gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
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gic_msi->length = sizeof(*gic_msi);
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gic_msi->gic_msi_frame_id = 0;
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gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
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gic_msi->flags = cpu_to_le32(1);
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gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
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gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
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}
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build_header(linker, table_data,
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(void *)(table_data->data + madt_start), "APIC",
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124
hw/arm/virt.c
124
hw/arm/virt.c
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@ -51,6 +51,7 @@
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#include "hw/intc/arm_gic_common.h"
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#include "kvm_arm.h"
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#include "hw/smbios/smbios.h"
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#include "qapi/visitor.h"
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/* Number of external interrupt lines to configure the GIC with */
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#define NUM_IRQS 256
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@ -81,6 +82,7 @@ typedef struct {
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MachineState parent;
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bool secure;
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bool highmem;
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int32_t gic_version;
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} VirtMachineState;
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#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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@ -111,6 +113,10 @@ static const MemMapEntry a15memmap[] = {
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[VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
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[VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
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[VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
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/* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
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[VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
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/* This redistributor space allows up to 2*64kB*123 CPUs */
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[VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
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[VIRT_UART] = { 0x09000000, 0x00001000 },
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[VIRT_RTC] = { 0x09010000, 0x00001000 },
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[VIRT_FW_CFG] = { 0x09020000, 0x0000000a },
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@ -255,7 +261,7 @@ static void fdt_add_psci_node(const VirtBoardInfo *vbi)
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qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
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}
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static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
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static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype)
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{
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/* Note that on A15 h/w these interrupts are level-triggered,
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* but for the GIC implementation provided by both QEMU and KVM
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@ -264,8 +270,11 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
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ARMCPU *armcpu;
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uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
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irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
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GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1);
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if (gictype == 2) {
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irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
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GIC_FDT_IRQ_PPI_CPU_WIDTH,
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(1 << vbi->smp_cpus) - 1);
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}
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qemu_fdt_add_subnode(vbi->fdt, "/timer");
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@ -355,25 +364,36 @@ static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
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qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle);
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}
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static void fdt_add_gic_node(VirtBoardInfo *vbi)
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static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
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{
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vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
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qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle);
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qemu_fdt_add_subnode(vbi->fdt, "/intc");
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/* 'cortex-a15-gic' means 'GIC v2' */
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qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
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"arm,cortex-a15-gic");
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3);
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qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
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2, vbi->memmap[VIRT_GIC_DIST].base,
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2, vbi->memmap[VIRT_GIC_DIST].size,
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2, vbi->memmap[VIRT_GIC_CPU].base,
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2, vbi->memmap[VIRT_GIC_CPU].size);
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2);
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qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0);
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if (type == 3) {
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qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
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"arm,gic-v3");
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qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
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2, vbi->memmap[VIRT_GIC_DIST].base,
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2, vbi->memmap[VIRT_GIC_DIST].size,
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2, vbi->memmap[VIRT_GIC_REDIST].base,
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2, vbi->memmap[VIRT_GIC_REDIST].size);
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} else {
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/* 'cortex-a15-gic' means 'GIC v2' */
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qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
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"arm,cortex-a15-gic");
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qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
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2, vbi->memmap[VIRT_GIC_DIST].base,
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2, vbi->memmap[VIRT_GIC_DIST].size,
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2, vbi->memmap[VIRT_GIC_CPU].base,
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2, vbi->memmap[VIRT_GIC_CPU].size);
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}
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
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}
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@ -396,18 +416,18 @@ static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
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fdt_add_v2m_gic_node(vbi);
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}
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static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, bool secure)
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static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure)
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{
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/* We create a standalone GIC v2 */
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/* We create a standalone GIC */
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DeviceState *gicdev;
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SysBusDevice *gicbusdev;
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const char *gictype;
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int i;
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gictype = gic_class_name();
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gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
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gicdev = qdev_create(NULL, gictype);
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qdev_prop_set_uint32(gicdev, "revision", 2);
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qdev_prop_set_uint32(gicdev, "revision", type);
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qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
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/* Note that the num-irq property counts both internal and external
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* interrupts; there are always 32 of the former (mandated by GIC spec).
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@ -419,7 +439,11 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, bool secure)
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qdev_init_nofail(gicdev);
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gicbusdev = SYS_BUS_DEVICE(gicdev);
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sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
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sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
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if (type == 3) {
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sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base);
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} else {
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sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
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}
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/* Wire the outputs from each CPU's generic timer to the
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* appropriate GIC PPI inputs, and the GIC's IRQ output to
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@ -454,9 +478,11 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, bool secure)
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pic[i] = qdev_get_gpio_in(gicdev, i);
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}
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fdt_add_gic_node(vbi);
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fdt_add_gic_node(vbi, type);
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create_v2m(vbi, pic);
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if (type == 2) {
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create_v2m(vbi, pic);
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}
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}
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static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
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@ -773,7 +799,10 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
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qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0,
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nr_pcie_buses - 1);
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qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", vbi->v2m_phandle);
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if (vbi->v2m_phandle) {
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qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent",
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vbi->v2m_phandle);
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}
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qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
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2, base_ecam, 2, size_ecam);
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@ -888,6 +917,7 @@ static void machvirt_init(MachineState *machine)
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VirtMachineState *vms = VIRT_MACHINE(machine);
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qemu_irq pic[NUM_IRQS];
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MemoryRegion *sysmem = get_system_memory();
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int gic_version = vms->gic_version;
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int n;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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const char *cpu_model = machine->cpu_model;
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@ -900,6 +930,18 @@ static void machvirt_init(MachineState *machine)
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cpu_model = "cortex-a15";
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}
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/* We can probe only here because during property set
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* KVM is not available yet
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*/
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if (!gic_version) {
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gic_version = kvm_arm_vgic_probe();
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if (!gic_version) {
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error_report("Unable to determine GIC version supported by host\n"
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"Probably KVM acceleration is not supported\n");
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exit(1);
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}
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}
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/* Separate the actual CPU model name from any appended features */
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cpustr = g_strsplit(cpu_model, ",", 2);
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@ -960,7 +1002,7 @@ static void machvirt_init(MachineState *machine)
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object_property_set_bool(cpuobj, true, "realized", NULL);
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}
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g_strfreev(cpustr);
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fdt_add_timer_nodes(vbi);
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fdt_add_timer_nodes(vbi, gic_version);
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fdt_add_cpu_nodes(vbi);
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fdt_add_psci_node(vbi);
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@ -970,7 +1012,7 @@ static void machvirt_init(MachineState *machine)
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create_flash(vbi);
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create_gic(vbi, pic, vms->secure);
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create_gic(vbi, pic, gic_version, vms->secure);
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create_uart(vbi, pic);
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@ -992,6 +1034,7 @@ static void machvirt_init(MachineState *machine)
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guest_info->memmap = vbi->memmap;
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guest_info->irqmap = vbi->irqmap;
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guest_info->use_highmem = vms->highmem;
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guest_info->gic_version = gic_version;
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guest_info_state->machine_done.notify = virt_guest_info_machine_done;
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qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
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@ -1043,6 +1086,31 @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
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vms->highmem = value;
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}
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static char *virt_get_gic_version(Object *obj, Error **errp)
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{
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VirtMachineState *vms = VIRT_MACHINE(obj);
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const char *val = vms->gic_version == 3 ? "3" : "2";
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return g_strdup(val);
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}
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static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
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{
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VirtMachineState *vms = VIRT_MACHINE(obj);
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if (!strcmp(value, "3")) {
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vms->gic_version = 3;
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} else if (!strcmp(value, "2")) {
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vms->gic_version = 2;
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} else if (!strcmp(value, "host")) {
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vms->gic_version = 0; /* Will probe later */
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} else {
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error_report("Invalid gic-version option value\n"
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"Allowed values are: 3, 2, host\n");
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exit(1);
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}
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}
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static void virt_instance_init(Object *obj)
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{
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VirtMachineState *vms = VIRT_MACHINE(obj);
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@ -1067,6 +1135,13 @@ static void virt_instance_init(Object *obj)
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"Set on/off to enable/disable using "
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"physical address space above 32 bits",
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NULL);
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/* Default GIC type is v2 */
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vms->gic_version = 2;
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object_property_add_str(obj, "gic-version", virt_get_gic_version,
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virt_set_gic_version, NULL);
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object_property_set_description(obj, "gic-version",
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"Set GIC version. "
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"Valid values are 2, 3 and host", NULL);
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}
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static void virt_class_init(ObjectClass *oc, void *data)
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@ -1075,7 +1150,10 @@ static void virt_class_init(ObjectClass *oc, void *data)
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mc->desc = "ARM Virtual Machine",
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mc->init = machvirt_init;
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mc->max_cpus = 8;
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/* Our maximum number of CPUs depends on how many redistributors
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* we can fit into memory map
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*/
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mc->max_cpus = a15memmap[VIRT_GIC_REDIST].size / 0x20000;
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mc->has_dynamic_sysbus = true;
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mc->block_default_type = IF_VIRTIO;
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mc->no_cdrom = 1;
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@ -384,6 +384,15 @@ struct AcpiMadtGenericMsiFrame {
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typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
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struct AcpiMadtGenericRedistributor {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint64_t base_address;
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uint32_t range_length;
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} QEMU_PACKED;
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typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
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/*
|
||||
* Generic Timer Description Table (GTDT)
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ typedef struct VirtGuestInfo {
|
|||
const MemMapEntry *memmap;
|
||||
const int *irqmap;
|
||||
bool use_highmem;
|
||||
int gic_version;
|
||||
} VirtGuestInfo;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -46,6 +46,9 @@ enum {
|
|||
VIRT_CPUPERIPHS,
|
||||
VIRT_GIC_DIST,
|
||||
VIRT_GIC_CPU,
|
||||
VIRT_GIC_V2M,
|
||||
VIRT_GIC_ITS,
|
||||
VIRT_GIC_REDIST,
|
||||
VIRT_UART,
|
||||
VIRT_MMIO,
|
||||
VIRT_RTC,
|
||||
|
|
@ -54,7 +57,6 @@ enum {
|
|||
VIRT_PCIE_MMIO,
|
||||
VIRT_PCIE_PIO,
|
||||
VIRT_PCIE_ECAM,
|
||||
VIRT_GIC_V2M,
|
||||
VIRT_PLATFORM_BUS,
|
||||
VIRT_PCIE_MMIO_HIGH,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue