ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

pl031: Rename pl031_state to PL031State 

Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-07-27 15:07:44 +02:00
parent b564b137b9
commit b91f0dfd12
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
hw/timer/pl031.c
View File

@ -33,7 +33,7 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
#define RTC_MIS 0x18 /* Masked interrupt status register */ #define RTC_MIS 0x18 /* Masked interrupt status register */
#define RTC_ICR 0x1c /* Interrupt clear register */ #define RTC_ICR 0x1c /* Interrupt clear register */
typedef struct { typedef struct PL031State {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion iomem; MemoryRegion iomem;
QEMUTimer *timer; QEMUTimer *timer;
@ -51,34 +51,34 @@ typedef struct {
uint32_t cr; uint32_t cr;
uint32_t im; uint32_t im;
uint32_t is; uint32_t is;
} pl031_state; } PL031State;
static const unsigned char pl031_id[] = { static const unsigned char pl031_id[] = {
0x31, 0x10, 0x14, 0x00, /* Device ID */ 0x31, 0x10, 0x14, 0x00, /* Device ID */
0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
}; };
static void pl031_update(pl031_state *s) static void pl031_update(PL031State *s)
{ {
qemu_set_irq(s->irq, s->is & s->im); qemu_set_irq(s->irq, s->is & s->im);
} }
static void pl031_interrupt(void * opaque) static void pl031_interrupt(void * opaque)
{ {
pl031_state *s = (pl031_state *)opaque; PL031State *s = (PL031State *)opaque;
s->is = 1; s->is = 1;
DPRINTF("Alarm raised\n"); DPRINTF("Alarm raised\n");
pl031_update(s); pl031_update(s);
} }
static uint32_t pl031_get_count(pl031_state *s) static uint32_t pl031_get_count(PL031State *s)
{ {
int64_t now = qemu_get_clock_ns(rtc_clock); int64_t now = qemu_get_clock_ns(rtc_clock);
return s->tick_offset + now / get_ticks_per_sec(); return s->tick_offset + now / get_ticks_per_sec();
} }
static void pl031_set_alarm(pl031_state *s) static void pl031_set_alarm(PL031State *s)
{ {
uint32_t ticks; uint32_t ticks;
@ -98,7 +98,7 @@ static void pl031_set_alarm(pl031_state *s)
static uint64_t pl031_read(void *opaque, hwaddr offset, static uint64_t pl031_read(void *opaque, hwaddr offset,
unsigned size) unsigned size)
{ {
pl031_state *s = (pl031_state *)opaque; PL031State *s = (PL031State *)opaque;
if (offset >= 0xfe0 && offset < 0x1000) if (offset >= 0xfe0 && offset < 0x1000)
return pl031_id[(offset - 0xfe0) >> 2]; return pl031_id[(offset - 0xfe0) >> 2];
@ -136,7 +136,7 @@ static uint64_t pl031_read(void *opaque, hwaddr offset,
static void pl031_write(void * opaque, hwaddr offset, static void pl031_write(void * opaque, hwaddr offset,
uint64_t value, unsigned size) uint64_t value, unsigned size)
{ {
pl031_state *s = (pl031_state *)opaque; PL031State *s = (PL031State *)opaque;
switch (offset) { switch (offset) {
@ -189,7 +189,7 @@ static const MemoryRegionOps pl031_ops = {
static int pl031_init(SysBusDevice *dev) static int pl031_init(SysBusDevice *dev)
{ {
pl031_state *s = FROM_SYSBUS(pl031_state, dev); PL031State *s = FROM_SYSBUS(PL031State, dev);
struct tm tm; struct tm tm;
memory_region_init_io(&s->iomem, OBJECT(s), &pl031_ops, s, "pl031", 0x1000); memory_region_init_io(&s->iomem, OBJECT(s), &pl031_ops, s, "pl031", 0x1000);
@ -205,7 +205,7 @@ static int pl031_init(SysBusDevice *dev)
static void pl031_pre_save(void *opaque) static void pl031_pre_save(void *opaque)
{ {
pl031_state *s = opaque; PL031State *s = opaque;
/* tick_offset is base_time - rtc_clock base time. Instead, we want to /* tick_offset is base_time - rtc_clock base time. Instead, we want to
* store the base time relative to the vm_clock for backwards-compatibility. */ * store the base time relative to the vm_clock for backwards-compatibility. */
@ -215,7 +215,7 @@ static void pl031_pre_save(void *opaque)
static int pl031_post_load(void *opaque, int version_id) static int pl031_post_load(void *opaque, int version_id)
{ {
pl031_state *s = opaque; PL031State *s = opaque;
int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec(); s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
@ -230,12 +230,12 @@ static const VMStateDescription vmstate_pl031 = {
.pre_save = pl031_pre_save, .pre_save = pl031_pre_save,
.post_load = pl031_post_load, .post_load = pl031_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT32(tick_offset_vmstate, pl031_state), VMSTATE_UINT32(tick_offset_vmstate, PL031State),
VMSTATE_UINT32(mr, pl031_state), VMSTATE_UINT32(mr, PL031State),
VMSTATE_UINT32(lr, pl031_state), VMSTATE_UINT32(lr, PL031State),
VMSTATE_UINT32(cr, pl031_state), VMSTATE_UINT32(cr, PL031State),
VMSTATE_UINT32(im, pl031_state), VMSTATE_UINT32(im, PL031State),
VMSTATE_UINT32(is, pl031_state), VMSTATE_UINT32(is, PL031State),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -253,7 +253,7 @@ static void pl031_class_init(ObjectClass *klass, void *data)
static const TypeInfo pl031_info = { static const TypeInfo pl031_info = {
.name = "pl031", .name = "pl031",
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl031_state), .instance_size = sizeof(PL031State),
.class_init = pl031_class_init, .class_init = pl031_class_init,
}; };