mirror of https://github.com/xemu-project/xemu.git
tcg: Push tcg_ctx into generator functions
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
6349039d0b
commit
b7e8b17a77
47
tcg/tcg-op.c
47
tcg/tcg-op.c
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@ -46,8 +46,9 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
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Up to and including filling in the forward link immediately. We'll do
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Up to and including filling in the forward link immediately. We'll do
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proper termination of the end of the list after we finish translation. */
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proper termination of the end of the list after we finish translation. */
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static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc)
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static inline TCGOp *tcg_emit_op(TCGOpcode opc)
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{
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{
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TCGContext *ctx = &tcg_ctx;
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int oi = ctx->gen_next_op_idx;
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int oi = ctx->gen_next_op_idx;
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int ni = oi + 1;
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int ni = oi + 1;
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int pi = oi - 1;
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int pi = oi - 1;
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@ -65,42 +66,40 @@ static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc)
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return op;
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return op;
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}
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}
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void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1)
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void tcg_gen_op1(TCGOpcode opc, TCGArg a1)
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{
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{
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TCGOp *op = tcg_emit_op(ctx, opc);
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TCGOp *op = tcg_emit_op(opc);
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op->args[0] = a1;
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op->args[0] = a1;
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}
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}
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void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2)
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void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
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{
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{
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TCGOp *op = tcg_emit_op(ctx, opc);
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TCGOp *op = tcg_emit_op(opc);
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op->args[0] = a1;
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[1] = a2;
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}
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}
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void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
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TCGArg a2, TCGArg a3)
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{
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{
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TCGOp *op = tcg_emit_op(ctx, opc);
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TCGOp *op = tcg_emit_op(opc);
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op->args[0] = a1;
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[2] = a3;
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}
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}
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void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
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TCGArg a2, TCGArg a3, TCGArg a4)
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{
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{
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TCGOp *op = tcg_emit_op(ctx, opc);
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TCGOp *op = tcg_emit_op(opc);
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op->args[0] = a1;
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[2] = a3;
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op->args[3] = a4;
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op->args[3] = a4;
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}
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}
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void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
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TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5)
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TCGArg a4, TCGArg a5)
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{
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{
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TCGOp *op = tcg_emit_op(ctx, opc);
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TCGOp *op = tcg_emit_op(opc);
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op->args[0] = a1;
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[2] = a3;
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@ -108,10 +107,10 @@ void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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op->args[4] = a5;
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op->args[4] = a5;
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}
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}
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void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
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void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
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TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6)
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TCGArg a4, TCGArg a5, TCGArg a6)
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{
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{
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TCGOp *op = tcg_emit_op(ctx, opc);
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TCGOp *op = tcg_emit_op(opc);
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op->args[0] = a1;
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[2] = a3;
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@ -123,7 +122,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
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void tcg_gen_mb(TCGBar mb_type)
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void tcg_gen_mb(TCGBar mb_type)
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{
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{
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if (parallel_cpus) {
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if (parallel_cpus) {
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tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type);
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tcg_gen_op1(INDEX_op_mb, mb_type);
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}
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}
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}
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}
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@ -2458,7 +2457,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
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if (TCG_TARGET_REG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_gen_mov_i32(ret, TCGV_LOW(arg));
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tcg_gen_mov_i32(ret, TCGV_LOW(arg));
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} else if (TCG_TARGET_HAS_extrl_i64_i32) {
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} else if (TCG_TARGET_HAS_extrl_i64_i32) {
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tcg_gen_op2(&tcg_ctx, INDEX_op_extrl_i64_i32,
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tcg_gen_op2(INDEX_op_extrl_i64_i32,
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GET_TCGV_I32(ret), GET_TCGV_I64(arg));
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GET_TCGV_I32(ret), GET_TCGV_I64(arg));
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} else {
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} else {
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tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
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tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
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@ -2470,7 +2469,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
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if (TCG_TARGET_REG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_gen_mov_i32(ret, TCGV_HIGH(arg));
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tcg_gen_mov_i32(ret, TCGV_HIGH(arg));
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} else if (TCG_TARGET_HAS_extrh_i64_i32) {
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} else if (TCG_TARGET_HAS_extrh_i64_i32) {
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tcg_gen_op2(&tcg_ctx, INDEX_op_extrh_i64_i32,
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tcg_gen_op2(INDEX_op_extrh_i64_i32,
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GET_TCGV_I32(ret), GET_TCGV_I64(arg));
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GET_TCGV_I32(ret), GET_TCGV_I64(arg));
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} else {
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} else {
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TCGv_i64 t = tcg_temp_new_i64();
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TCGv_i64 t = tcg_temp_new_i64();
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@ -2486,7 +2485,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
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tcg_gen_mov_i32(TCGV_LOW(ret), arg);
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tcg_gen_mov_i32(TCGV_LOW(ret), arg);
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tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
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tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
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} else {
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} else {
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tcg_gen_op2(&tcg_ctx, INDEX_op_extu_i32_i64,
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tcg_gen_op2(INDEX_op_extu_i32_i64,
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GET_TCGV_I64(ret), GET_TCGV_I32(arg));
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GET_TCGV_I64(ret), GET_TCGV_I32(arg));
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}
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}
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}
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}
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@ -2497,7 +2496,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
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tcg_gen_mov_i32(TCGV_LOW(ret), arg);
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tcg_gen_mov_i32(TCGV_LOW(ret), arg);
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tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
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tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
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} else {
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} else {
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tcg_gen_op2(&tcg_ctx, INDEX_op_ext_i32_i64,
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tcg_gen_op2(INDEX_op_ext_i32_i64,
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GET_TCGV_I64(ret), GET_TCGV_I32(arg));
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GET_TCGV_I64(ret), GET_TCGV_I32(arg));
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}
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}
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}
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}
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@ -2609,7 +2608,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
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if (TCG_TARGET_REG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi);
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tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi);
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} else {
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} else {
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tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi);
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tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi);
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}
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}
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#endif
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#endif
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}
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}
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@ -2622,7 +2621,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
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if (TCG_TARGET_REG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
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tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
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} else {
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} else {
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tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi);
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tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi);
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}
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}
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#else
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#else
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if (TCG_TARGET_REG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 32) {
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100
tcg/tcg-op.h
100
tcg/tcg-op.h
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@ -28,173 +28,166 @@
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/* Basic output routines. Not for general consumption. */
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/* Basic output routines. Not for general consumption. */
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void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
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void tcg_gen_op1(TCGOpcode, TCGArg);
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void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
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void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
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void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);
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void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
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void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
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void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
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void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
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void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
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TCGArg, TCGArg);
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void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
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void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
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TCGArg, TCGArg, TCGArg);
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
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{
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{
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tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1));
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tcg_gen_op1(opc, GET_TCGV_I32(a1));
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}
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}
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
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{
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{
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tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1));
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tcg_gen_op1(opc, GET_TCGV_I64(a1));
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}
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}
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
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{
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{
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tcg_gen_op1(&tcg_ctx, opc, a1);
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tcg_gen_op1(opc, a1);
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}
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}
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
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{
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{
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tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
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tcg_gen_op2(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
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}
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}
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
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{
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{
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tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
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tcg_gen_op2(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
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}
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}
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
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{
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{
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tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2);
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tcg_gen_op2(opc, GET_TCGV_I32(a1), a2);
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}
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}
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
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{
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{
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tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2);
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tcg_gen_op2(opc, GET_TCGV_I64(a1), a2);
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}
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}
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
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{
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{
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tcg_gen_op2(&tcg_ctx, opc, a1, a2);
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tcg_gen_op2(opc, a1, a2);
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}
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}
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
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TCGv_i32 a2, TCGv_i32 a3)
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TCGv_i32 a2, TCGv_i32 a3)
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{
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{
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tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1),
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tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3));
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GET_TCGV_I32(a2), GET_TCGV_I32(a3));
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}
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}
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
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TCGv_i64 a2, TCGv_i64 a3)
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TCGv_i64 a2, TCGv_i64 a3)
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{
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{
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tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1),
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tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3));
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GET_TCGV_I64(a2), GET_TCGV_I64(a3));
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}
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}
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
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TCGv_i32 a2, TCGArg a3)
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TCGv_i32 a2, TCGArg a3)
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{
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{
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tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
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tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
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}
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}
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
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TCGv_i64 a2, TCGArg a3)
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TCGv_i64 a2, TCGArg a3)
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{
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{
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tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
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tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
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}
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}
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|
||||||
static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
|
static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
|
||||||
TCGv_ptr base, TCGArg offset)
|
TCGv_ptr base, TCGArg offset)
|
||||||
{
|
{
|
||||||
tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
|
tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
|
static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
|
||||||
TCGv_ptr base, TCGArg offset)
|
TCGv_ptr base, TCGArg offset)
|
||||||
{
|
{
|
||||||
tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
|
tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGv_i32 a4)
|
TCGv_i32 a3, TCGv_i32 a4)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), GET_TCGV_I32(a4));
|
GET_TCGV_I32(a3), GET_TCGV_I32(a4));
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGv_i64 a4)
|
TCGv_i64 a3, TCGv_i64 a4)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), GET_TCGV_I64(a4));
|
GET_TCGV_I64(a3), GET_TCGV_I64(a4));
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGArg a4)
|
TCGv_i32 a3, TCGArg a4)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4);
|
||||||
GET_TCGV_I32(a3), a4);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGArg a4)
|
TCGv_i64 a3, TCGArg a4)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4);
|
||||||
GET_TCGV_I64(a3), a4);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGArg a3, TCGArg a4)
|
TCGArg a3, TCGArg a4)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
|
tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGArg a3, TCGArg a4)
|
TCGArg a3, TCGArg a4)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
|
tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
|
TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
|
||||||
{
|
{
|
||||||
tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
|
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
|
TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
|
||||||
{
|
{
|
||||||
tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
|
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
|
TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
|
||||||
{
|
{
|
||||||
tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
|
GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
|
TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
|
||||||
{
|
{
|
||||||
tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
|
GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGArg a4, TCGArg a5)
|
TCGv_i32 a3, TCGArg a4, TCGArg a5)
|
||||||
{
|
{
|
||||||
tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), a4, a5);
|
GET_TCGV_I32(a3), a4, a5);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGArg a4, TCGArg a5)
|
TCGv_i64 a3, TCGArg a4, TCGArg a5)
|
||||||
{
|
{
|
||||||
tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), a4, a5);
|
GET_TCGV_I64(a3), a4, a5);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -202,7 +195,7 @@ static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGv_i32 a4,
|
TCGv_i32 a3, TCGv_i32 a4,
|
||||||
TCGv_i32 a5, TCGv_i32 a6)
|
TCGv_i32 a5, TCGv_i32 a6)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
|
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
|
||||||
GET_TCGV_I32(a6));
|
GET_TCGV_I32(a6));
|
||||||
}
|
}
|
||||||
|
@ -211,7 +204,7 @@ static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGv_i64 a4,
|
TCGv_i64 a3, TCGv_i64 a4,
|
||||||
TCGv_i64 a5, TCGv_i64 a6)
|
TCGv_i64 a5, TCGv_i64 a6)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
|
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
|
||||||
GET_TCGV_I64(a6));
|
GET_TCGV_I64(a6));
|
||||||
}
|
}
|
||||||
|
@ -220,7 +213,7 @@ static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGv_i32 a4,
|
TCGv_i32 a3, TCGv_i32 a4,
|
||||||
TCGv_i32 a5, TCGArg a6)
|
TCGv_i32 a5, TCGArg a6)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
|
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -228,7 +221,7 @@ static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGv_i64 a4,
|
TCGv_i64 a3, TCGv_i64 a4,
|
||||||
TCGv_i64 a5, TCGArg a6)
|
TCGv_i64 a5, TCGArg a6)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
|
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -236,7 +229,7 @@ static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
|
||||||
TCGv_i32 a3, TCGv_i32 a4,
|
TCGv_i32 a3, TCGv_i32 a4,
|
||||||
TCGArg a5, TCGArg a6)
|
TCGArg a5, TCGArg a6)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
|
||||||
GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
|
GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -244,7 +237,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
TCGv_i64 a3, TCGv_i64 a4,
|
TCGv_i64 a3, TCGv_i64 a4,
|
||||||
TCGArg a5, TCGArg a6)
|
TCGArg a5, TCGArg a6)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
|
||||||
GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
|
GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -253,12 +246,12 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
|
||||||
|
|
||||||
static inline void gen_set_label(TCGLabel *l)
|
static inline void gen_set_label(TCGLabel *l)
|
||||||
{
|
{
|
||||||
tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l));
|
tcg_gen_op1(INDEX_op_set_label, label_arg(l));
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void tcg_gen_br(TCGLabel *l)
|
static inline void tcg_gen_br(TCGLabel *l)
|
||||||
{
|
{
|
||||||
tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
|
tcg_gen_op1(INDEX_op_br, label_arg(l));
|
||||||
}
|
}
|
||||||
|
|
||||||
void tcg_gen_mb(TCGBar);
|
void tcg_gen_mb(TCGBar);
|
||||||
|
@ -732,25 +725,24 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
|
||||||
# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
|
# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
|
||||||
static inline void tcg_gen_insn_start(target_ulong pc)
|
static inline void tcg_gen_insn_start(target_ulong pc)
|
||||||
{
|
{
|
||||||
tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc);
|
tcg_gen_op1(INDEX_op_insn_start, pc);
|
||||||
}
|
}
|
||||||
# else
|
# else
|
||||||
static inline void tcg_gen_insn_start(target_ulong pc)
|
static inline void tcg_gen_insn_start(target_ulong pc)
|
||||||
{
|
{
|
||||||
tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start,
|
tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
|
||||||
(uint32_t)pc, (uint32_t)(pc >> 32));
|
|
||||||
}
|
}
|
||||||
# endif
|
# endif
|
||||||
#elif TARGET_INSN_START_WORDS == 2
|
#elif TARGET_INSN_START_WORDS == 2
|
||||||
# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
|
# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
|
||||||
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
|
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
|
||||||
{
|
{
|
||||||
tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1);
|
tcg_gen_op2(INDEX_op_insn_start, pc, a1);
|
||||||
}
|
}
|
||||||
# else
|
# else
|
||||||
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
|
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
|
||||||
{
|
{
|
||||||
tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start,
|
tcg_gen_op4(INDEX_op_insn_start,
|
||||||
(uint32_t)pc, (uint32_t)(pc >> 32),
|
(uint32_t)pc, (uint32_t)(pc >> 32),
|
||||||
(uint32_t)a1, (uint32_t)(a1 >> 32));
|
(uint32_t)a1, (uint32_t)(a1 >> 32));
|
||||||
}
|
}
|
||||||
|
@ -760,13 +752,13 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
|
||||||
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
|
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
|
||||||
target_ulong a2)
|
target_ulong a2)
|
||||||
{
|
{
|
||||||
tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
|
tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
|
||||||
}
|
}
|
||||||
# else
|
# else
|
||||||
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
|
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
|
||||||
target_ulong a2)
|
target_ulong a2)
|
||||||
{
|
{
|
||||||
tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start,
|
tcg_gen_op6(INDEX_op_insn_start,
|
||||||
(uint32_t)pc, (uint32_t)(pc >> 32),
|
(uint32_t)pc, (uint32_t)(pc >> 32),
|
||||||
(uint32_t)a1, (uint32_t)(a1 >> 32),
|
(uint32_t)a1, (uint32_t)(a1 >> 32),
|
||||||
(uint32_t)a2, (uint32_t)(a2 >> 32));
|
(uint32_t)a2, (uint32_t)(a2 >> 32));
|
||||||
|
|
Loading…
Reference in New Issue