ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Remove unnecessary cast when using the address_space API 

This commit was produced with the included Coccinelle script
scripts/coccinelle/exec_rw_const.

Two lines in hw/net/dp8393x.c that Coccinelle produced that
were over 80 characters were re-wrapped by hand.

Suggested-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2020-02-19 20:28:22 +01:00
parent 4ef044cb14
commit b7cbebf2b9
12 changed files with 54 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hw/arm/boot.c
View File

@ -327,8 +327,7 @@ static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
cmdline_size = strlen(info->kernel_cmdline); cmdline_size = strlen(info->kernel_cmdline);
address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
(const uint8_t *)info->kernel_cmdline, info->kernel_cmdline, cmdline_size + 1);
cmdline_size + 1);
cmdline_size = (cmdline_size >> 2) + 1; cmdline_size = (cmdline_size >> 2) + 1;
WRITE_WORD(p, cmdline_size + 2); WRITE_WORD(p, cmdline_size + 2);
WRITE_WORD(p, 0x54410009); WRITE_WORD(p, 0x54410009);
@ -420,8 +419,7 @@ static void set_kernel_args_old(const struct arm_boot_info *info,
} }
s = info->kernel_cmdline; s = info->kernel_cmdline;
if (s) { if (s) {
address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
(const uint8_t *)s, strlen(s) + 1);
} else { } else {
WRITE_WORD(p, 0); WRITE_WORD(p, 0);
} }

4
hw/dma/rc4030.c
View File

@ -513,8 +513,8 @@ static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
if (i < s->dma_tl_limit / sizeof(entry)) { if (i < s->dma_tl_limit / sizeof(entry)) {
entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
if (address_space_read(ret.target_as, entry_address, if (address_space_read(ret.target_as, entry_address,
MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry, MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry))
sizeof(entry)) == MEMTX_OK) { == MEMTX_OK) {
ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
ret.perm = IOMMU_RW; ret.perm = IOMMU_RW;
} }

2
hw/dma/xlnx-zdma.c
View File

@ -364,7 +364,7 @@ static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
} else { } else {
addr = zdma_get_regaddr64(s, basereg); addr = zdma_get_regaddr64(s, basereg);
addr += sizeof(s->dsc_dst); addr += sizeof(s->dsc_dst);
address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, false); address_space_rw(s->dma_as, addr, s->attr, &next, 8, false);
zdma_put_regaddr64(s, basereg, next); zdma_put_regaddr64(s, basereg, next);
} }
return next; return next;

17
hw/net/cadence_gem.c
View File

@ -871,7 +871,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
/* read current descriptor */ /* read current descriptor */
address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)s->rx_desc[q], s->rx_desc[q],
sizeof(uint32_t) * gem_get_desc_len(s, true)); sizeof(uint32_t) * gem_get_desc_len(s, true));
/* Descriptor owned by software ? */ /* Descriptor owned by software ? */
@ -1029,9 +1029,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Descriptor write-back. */ /* Descriptor write-back. */
desc_addr = gem_get_rx_desc_addr(s, q); desc_addr = gem_get_rx_desc_addr(s, q);
address_space_write(&s->dma_as, desc_addr, address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
MEMTXATTRS_UNSPECIFIED, s->rx_desc[q],
(uint8_t *)s->rx_desc[q],
sizeof(uint32_t) * gem_get_desc_len(s, true)); sizeof(uint32_t) * gem_get_desc_len(s, true));
/* Next descriptor */ /* Next descriptor */
@ -1137,7 +1136,7 @@ static void gem_transmit(CadenceGEMState *s)
DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
address_space_read(&s->dma_as, packet_desc_addr, address_space_read(&s->dma_as, packet_desc_addr,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, MEMTXATTRS_UNSPECIFIED, desc,
sizeof(uint32_t) * gem_get_desc_len(s, false)); sizeof(uint32_t) * gem_get_desc_len(s, false));
/* Handle all descriptors owned by hardware */ /* Handle all descriptors owned by hardware */
while (tx_desc_get_used(desc) == 0) { while (tx_desc_get_used(desc) == 0) {
@ -1185,13 +1184,11 @@ static void gem_transmit(CadenceGEMState *s)
* the processor. * the processor.
*/ */
address_space_read(&s->dma_as, desc_addr, address_space_read(&s->dma_as, desc_addr,
MEMTXATTRS_UNSPECIFIED, MEMTXATTRS_UNSPECIFIED, desc_first,
(uint8_t *)desc_first,
sizeof(desc_first)); sizeof(desc_first));
tx_desc_set_used(desc_first); tx_desc_set_used(desc_first);
address_space_write(&s->dma_as, desc_addr, address_space_write(&s->dma_as, desc_addr,
MEMTXATTRS_UNSPECIFIED, MEMTXATTRS_UNSPECIFIED, desc_first,
(uint8_t *)desc_first,
sizeof(desc_first)); sizeof(desc_first));
/* Advance the hardware current descriptor past this packet */ /* Advance the hardware current descriptor past this packet */
if (tx_desc_get_wrap(desc)) { if (tx_desc_get_wrap(desc)) {
@ -1246,7 +1243,7 @@ static void gem_transmit(CadenceGEMState *s)
} }
DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
address_space_read(&s->dma_as, packet_desc_addr, address_space_read(&s->dma_as, packet_desc_addr,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, MEMTXATTRS_UNSPECIFIED, desc,
sizeof(uint32_t) * gem_get_desc_len(s, false)); sizeof(uint32_t) * gem_get_desc_len(s, false));
} }

24
hw/net/dp8393x.c
View File

@ -276,7 +276,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
while (s->regs[SONIC_CDC] & 0x1f) { while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */ /* Fill current entry */
address_space_rw(&s->as, dp8393x_cdp(s), address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
@ -294,7 +294,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Read CAM enable */ /* Read CAM enable */
address_space_rw(&s->as, dp8393x_cdp(s), address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_CE] = dp8393x_get(s, width, 0); s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
@ -312,7 +312,7 @@ static void dp8393x_do_read_rra(dp8393xState *s)
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width; size = sizeof(uint16_t) * 4 * width;
address_space_rw(&s->as, dp8393x_rrp(s), address_space_rw(&s->as, dp8393x_rrp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
/* Update SONIC registers */ /* Update SONIC registers */
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
@ -427,7 +427,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
tx_len = 0; tx_len = 0;
/* Update registers */ /* Update registers */
@ -461,7 +461,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * 3 * width; size = sizeof(uint16_t) * 3 * width;
address_space_rw(&s->as, address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
@ -496,7 +496,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * width; size = sizeof(uint16_t) * width;
address_space_rw(&s->as, address_space_rw(&s->as,
dp8393x_ttda(s), dp8393x_ttda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); MEMTXATTRS_UNSPECIFIED, s->data, size, 1);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */ /* Read footer of packet */
@ -505,7 +505,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
dp8393x_ttda(s) + dp8393x_ttda(s) +
sizeof(uint16_t) * sizeof(uint16_t) *
(4 + 3 * s->regs[SONIC_TFC]) * width, (4 + 3 * s->regs[SONIC_TFC]) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
if (dp8393x_get(s, width, 0) & 0x1) { if (dp8393x_get(s, width, 0) & 0x1) {
/* EOL detected */ /* EOL detected */
@ -768,7 +768,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * 1 * width; size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)s->data, size, 0); s->data, size, 0);
if (dp8393x_get(s, width, 0) & 0x1) { if (dp8393x_get(s, width, 0) & 0x1) {
/* Still EOL ; stop reception */ /* Still EOL ; stop reception */
return -1; return -1;
@ -790,7 +790,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len); address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len);
address += rx_len; address += rx_len;
address_space_rw(&s->as, address, address_space_rw(&s->as, address,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); MEMTXATTRS_UNSPECIFIED, &checksum, 4, 1);
rx_len += 4; rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16; s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff; s->regs[SONIC_CRBA0] = address & 0xffff;
@ -819,12 +819,12 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width; size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s), address_space_rw(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); MEMTXATTRS_UNSPECIFIED, s->data, size, 1);
/* Move to next descriptor */ /* Move to next descriptor */
size = sizeof(uint16_t) * width; size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
if (s->regs[SONIC_LLFA] & 0x1) { if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */ /* EOL detected */
@ -838,7 +838,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
} }
s->data[0] = 0; s->data[0] = 0;
address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)s->data, sizeof(uint16_t), 1); s->data, sizeof(uint16_t), 1);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);

4
hw/s390x/css.c
View File

@ -875,7 +875,7 @@ static inline int ida_read_next_idaw(CcwDataStream *cds)
return -EINVAL; /* channel program check */ return -EINVAL; /* channel program check */
} }
ret = address_space_rw(&address_space_memory, idaw_addr, ret = address_space_rw(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
sizeof(idaw.fmt2), false); sizeof(idaw.fmt2), false);
cds->cda = be64_to_cpu(idaw.fmt2); cds->cda = be64_to_cpu(idaw.fmt2);
} else { } else {
@ -884,7 +884,7 @@ static inline int ida_read_next_idaw(CcwDataStream *cds)
return -EINVAL; /* channel program check */ return -EINVAL; /* channel program check */
} }
ret = address_space_rw(&address_space_memory, idaw_addr, ret = address_space_rw(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
sizeof(idaw.fmt1), false); sizeof(idaw.fmt1), false);
cds->cda = be64_to_cpu(idaw.fmt1); cds->cda = be64_to_cpu(idaw.fmt1);
if (cds->cda & 0x80000000) { if (cds->cda & 0x80000000) {

12
qtest.c
View File

@ -435,17 +435,17 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
uint16_t data = value; uint16_t data = value;
tswap16s(&data); tswap16s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *) &data, 2, true); &data, 2, true);
} else if (words[0][5] == 'l') { } else if (words[0][5] == 'l') {
uint32_t data = value; uint32_t data = value;
tswap32s(&data); tswap32s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *) &data, 4, true); &data, 4, true);
} else if (words[0][5] == 'q') { } else if (words[0][5] == 'q') {
uint64_t data = value; uint64_t data = value;
tswap64s(&data); tswap64s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *) &data, 8, true); &data, 8, true);
} }
qtest_send_prefix(chr); qtest_send_prefix(chr);
qtest_send(chr, "OK\n"); qtest_send(chr, "OK\n");
@ -469,16 +469,16 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
} else if (words[0][4] == 'w') { } else if (words[0][4] == 'w') {
uint16_t data; uint16_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *) &data, 2, false); &data, 2, false);
value = tswap16(data); value = tswap16(data);
} else if (words[0][4] == 'l') { } else if (words[0][4] == 'l') {
uint32_t data; uint32_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *) &data, 4, false); &data, 4, false);
value = tswap32(data); value = tswap32(data);
} else if (words[0][4] == 'q') { } else if (words[0][4] == 'q') {
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *) &value, 8, false); &value, 8, false);
tswap64s(&value); tswap64s(&value);
} }
qtest_send_prefix(chr); qtest_send_prefix(chr);

15
scripts/coccinelle/exec_rw_const.cocci
View File

@ -25,10 +25,23 @@ expression E1, E2, E3, E4;
// Remove useless cast // Remove useless cast
@@ @@
expression E1, E2, E3, E4; expression E1, E2, E3, E4, E5, E6;
type T; type T;
@@ @@
( (
- address_space_rw(E1, E2, E3, (T *)(E4), E5, E6)
+ address_space_rw(E1, E2, E3, E4, E5, E6)
|
- address_space_read(E1, E2, E3, (T *)(E4), E5)
+ address_space_read(E1, E2, E3, E4, E5)
|
- address_space_write(E1, E2, E3, (T *)(E4), E5)
+ address_space_write(E1, E2, E3, E4, E5)
|
- address_space_write_rom(E1, E2, E3, (T *)(E4), E5)
+ address_space_write_rom(E1, E2, E3, E4, E5)
|
- dma_memory_read(E1, E2, (T *)(E3), E4) - dma_memory_read(E1, E2, (T *)(E3), E4)
+ dma_memory_read(E1, E2, E3, E4) + dma_memory_read(E1, E2, E3, E4)
| |

2
target/i386/hvf/vmx.h
View File

@ -128,7 +128,7 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
address_space_rw(&address_space_memory, address_space_rw(&address_space_memory,
rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
MEMTXATTRS_UNSPECIFIED, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)pdpte, 32, 0); pdpte, 32, 0);
/* Only set PDPTE when appropriate. */ /* Only set PDPTE when appropriate. */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);

2
target/i386/hvf/x86_mmu.c
View File

@ -89,7 +89,7 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
index = gpt_entry(pt->gva, level, pae); index = gpt_entry(pt->gva, level, pae);
address_space_rw(&address_space_memory, gpa + index * pte_size(pae), address_space_rw(&address_space_memory, gpa + index * pte_size(pae),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0); MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), 0);
pt->pte[level - 1] = pte; pt->pte[level - 1] = pte;

2
target/i386/whpx-all.c
View File

@ -540,7 +540,7 @@ static HRESULT CALLBACK whpx_emu_ioport_callback(
{ {
MemTxAttrs attrs = { 0 }; MemTxAttrs attrs = { 0 };
address_space_rw(&address_space_io, IoAccess->Port, attrs, address_space_rw(&address_space_io, IoAccess->Port, attrs,
(uint8_t *)&IoAccess->Data, IoAccess->AccessSize, &IoAccess->Data, IoAccess->AccessSize,
IoAccess->Direction); IoAccess->Direction);
return S_OK; return S_OK;
} }

2
target/s390x/mmu_helper.c
View File

@ -106,7 +106,7 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
* We treat them as absolute addresses and don't wrap them. * We treat them as absolute addresses and don't wrap them.
*/ */
if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)entry, sizeof(*entry)) != entry, sizeof(*entry)) !=
MEMTX_OK)) { MEMTX_OK)) {
return false; return false;
} }