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OpenRISC updates for 9.2.0 

This series has 2 fixes:
  - Fix to keep serial@90000000 as default
  - Fixed undercounting of TTCR in continuous mode
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmdO56EACgkQw7McLV5m
 J+T8BRAAxZMH4ykdRJBmYiFVOsYKagcdT6GGBHL44FGeQSr1lNyoU0Rn5r6v5GHe
 Nwq7DTeZlKoVji5GXki53mGrwENXr00m+xfc9ACMoWr5IM6McQUPXlQAQ/50fIGs
 lzXMZH/4EdPIVkkpCi+y8FLYw02oQg61U9G0HW02lQJy4Y4mudtvQFGzJ7f3SIZ3
 EkKn5YLG0bqszq/amFNLQXlbnq3yI5zfcMHhHx0KuDsm2yNhrNA+AJP8tLI3JlxL
 +0YIA+fWuxQzz8Zu9+ckc8VAV83HIgQpXVzI6rQxdSwbmRgUu9ITO09ZmxaDHZF6
 sDI6K3VouyaHJVkvu4coDajpYTjHLE26c9LAlaVBpgdnmnYy4vlndEqbfaBqOouX
 n0N2wJ3IGouIw7AnB9dTaZhM/Uo09hZKDr6kCm3hLfPn2+vi3yxsbwVwLaOpH3G3
 kQ5ZFKjoA7XWOaXGOUMcmhByXkSxja+pSBppB58vJAFyVp73HYIpea3/q1Zd8S4S
 noJoqxDtD2zf26bDBIe83pUEnSnL8fAcsh3rlQP8HrWYhU7ZulVSE1ZvPkPgDpkY
 LVCPautTElsMp2Mg4a2oODGvSDN4/5h2dp6TaK4Qep92HHFOwPZQBQW607VwWR5N
 II8dB/l8PluKkgZ3ymhP1p9JAAZFe9a2cMmegRIiM74PkPty0kk=
 =guIi
 -----END PGP SIGNATURE-----

Merge tag 'pull-or1k-20241203' of https://github.com/stffrdhrn/qemu into staging

OpenRISC updates for 9.2.0

This series has 2 fixes:
 - Fix to keep serial@90000000 as default
 - Fixed undercounting of TTCR in continuous mode

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmdO56EACgkQw7McLV5m
# J+T8BRAAxZMH4ykdRJBmYiFVOsYKagcdT6GGBHL44FGeQSr1lNyoU0Rn5r6v5GHe
# Nwq7DTeZlKoVji5GXki53mGrwENXr00m+xfc9ACMoWr5IM6McQUPXlQAQ/50fIGs
# lzXMZH/4EdPIVkkpCi+y8FLYw02oQg61U9G0HW02lQJy4Y4mudtvQFGzJ7f3SIZ3
# EkKn5YLG0bqszq/amFNLQXlbnq3yI5zfcMHhHx0KuDsm2yNhrNA+AJP8tLI3JlxL
# +0YIA+fWuxQzz8Zu9+ckc8VAV83HIgQpXVzI6rQxdSwbmRgUu9ITO09ZmxaDHZF6
# sDI6K3VouyaHJVkvu4coDajpYTjHLE26c9LAlaVBpgdnmnYy4vlndEqbfaBqOouX
# n0N2wJ3IGouIw7AnB9dTaZhM/Uo09hZKDr6kCm3hLfPn2+vi3yxsbwVwLaOpH3G3
# kQ5ZFKjoA7XWOaXGOUMcmhByXkSxja+pSBppB58vJAFyVp73HYIpea3/q1Zd8S4S
# noJoqxDtD2zf26bDBIe83pUEnSnL8fAcsh3rlQP8HrWYhU7ZulVSE1ZvPkPgDpkY
# LVCPautTElsMp2Mg4a2oODGvSDN4/5h2dp6TaK4Qep92HHFOwPZQBQW607VwWR5N
# II8dB/l8PluKkgZ3ymhP1p9JAAZFe9a2cMmegRIiM74PkPty0kk=
# =guIi
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 03 Dec 2024 11:12:33 GMT
# gpg:                using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* tag 'pull-or1k-20241203' of https://github.com/stffrdhrn/qemu:
  hw/openrisc: Fixed undercounting of TTCR in continuous mode
  hw/openrisc/openrisc_sim: keep serial@90000000 as default

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-12-03 13:43:57 +00:00
parent 248f9209ed 3eb43aeb16
commit b733701533
2 changed files with 35 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
hw/openrisc/cputimer.c
View File

@ -29,7 +29,8 @@
/* Tick Timer global state to allow all cores to be in sync */ /* Tick Timer global state to allow all cores to be in sync */
typedef struct OR1KTimerState { typedef struct OR1KTimerState {
uint32_t ttcr; uint32_t ttcr;
uint64_t last_clk; uint32_t ttcr_offset;
uint64_t clk_offset;
} OR1KTimerState; } OR1KTimerState;
static OR1KTimerState *or1k_timer; static OR1KTimerState *or1k_timer;
@ -37,6 +38,8 @@ static OR1KTimerState *or1k_timer;
void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val)
{ {
or1k_timer->ttcr = val; or1k_timer->ttcr = val;
or1k_timer->ttcr_offset = val;
or1k_timer->clk_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
} }
uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)
@ -53,9 +56,8 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu)
return; return;
} }
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk) or1k_timer->ttcr = or1k_timer->ttcr_offset +
/ TIMER_PERIOD); DIV_ROUND_UP(now - or1k_timer->clk_offset, TIMER_PERIOD);
or1k_timer->last_clk = now;
} }
/* Update the next timeout time as difference between ttmr and ttcr */ /* Update the next timeout time as difference between ttmr and ttcr */
@ -69,7 +71,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
} }
cpu_openrisc_count_update(cpu); cpu_openrisc_count_update(cpu);
now = or1k_timer->last_clk; now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) {
wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1;
@ -110,7 +112,8 @@ static void openrisc_timer_cb(void *opaque)
case TIMER_NONE: case TIMER_NONE:
break; break;
case TIMER_INTR: case TIMER_INTR:
or1k_timer->ttcr = 0; /* Zero the count by applying a negative offset to the counter */
or1k_timer->ttcr_offset -= (cpu->env.ttmr & TTMR_TP);
break; break;
case TIMER_SHOT: case TIMER_SHOT:
cpu_openrisc_count_stop(cpu); cpu_openrisc_count_stop(cpu);
@ -137,17 +140,18 @@ static void openrisc_count_reset(void *opaque)
/* Reset the global timer state. */ /* Reset the global timer state. */
static void openrisc_timer_reset(void *opaque) static void openrisc_timer_reset(void *opaque)
{ {
or1k_timer->ttcr = 0x00000000; OpenRISCCPU *cpu = opaque;
or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); cpu_openrisc_count_set(cpu, 0);
} }
static const VMStateDescription vmstate_or1k_timer = { static const VMStateDescription vmstate_or1k_timer = {
.name = "or1k_timer", .name = "or1k_timer",
.version_id = 1, .version_id = 2,
.minimum_version_id = 1, .minimum_version_id = 2,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_UINT32(ttcr, OR1KTimerState), VMSTATE_UINT32(ttcr, OR1KTimerState),
VMSTATE_UINT64(last_clk, OR1KTimerState), VMSTATE_UINT32(ttcr_offset, OR1KTimerState),
VMSTATE_UINT64(clk_offset, OR1KTimerState),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };

26
hw/openrisc/openrisc_sim.c
View File

@ -250,7 +250,7 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
void *fdt = state->fdt; void *fdt = state->fdt;
char *nodename; char *nodename;
qemu_irq serial_irq; qemu_irq serial_irq;
char alias[sizeof("uart0")]; char alias[sizeof("serial0")];
int i; int i;
if (num_cpus > 1) { if (num_cpus > 1) {
@ -265,7 +265,7 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
serial_irq = get_cpu_irq(cpus, 0, irq_pin); serial_irq = get_cpu_irq(cpus, 0, irq_pin);
} }
serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1), serial_hd(uart_idx),
DEVICE_NATIVE_ENDIAN); DEVICE_NATIVE_ENDIAN);
/* Add device tree node for serial. */ /* Add device tree node for serial. */
@ -277,10 +277,13 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);
qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
/* The /chosen node is created during fdt creation. */ if (uart_idx == 0) {
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); /* The /chosen node is created during fdt creation. */
snprintf(alias, sizeof(alias), "uart%d", uart_idx); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
}
snprintf(alias, sizeof(alias), "serial%d", uart_idx);
qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename); qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
g_free(nodename); g_free(nodename);
} }
@ -326,11 +329,22 @@ static void openrisc_sim_init(MachineState *machine)
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ); smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
} }
for (n = 0; n < OR1KSIM_UART_COUNT; ++n) /*
* We create the UART nodes starting with the highest address and
* working downwards, because in QEMU the DTB nodes end up in the
* DTB in reverse order of creation. Correctly-written guest software
* will not care about the node order (it will look at stdout-path
* or the alias nodes), but for the benefit of guest software which
* just looks for the first UART node in the DTB, make sure the
* lowest-address UART (which is QEMU's first serial port) appears
* first in the DTB.
*/
for (n = OR1KSIM_UART_COUNT - 1; n >= 0; n--) {
openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base + openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
or1ksim_memmap[OR1KSIM_UART].size * n, or1ksim_memmap[OR1KSIM_UART].size * n,
or1ksim_memmap[OR1KSIM_UART].size, or1ksim_memmap[OR1KSIM_UART].size,
smp_cpus, cpus, OR1KSIM_UART_IRQ, n); smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
}
load_addr = openrisc_load_kernel(ram_size, kernel_filename, load_addr = openrisc_load_kernel(ram_size, kernel_filename,
&boot_info.bootstrap_pc); &boot_info.bootstrap_pc);