mirror of https://github.com/xemu-project/xemu.git
OpenRISC updates for 9.2.0
This series has 2 fixes: - Fix to keep serial@90000000 as default - Fixed undercounting of TTCR in continuous mode -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmdO56EACgkQw7McLV5m J+T8BRAAxZMH4ykdRJBmYiFVOsYKagcdT6GGBHL44FGeQSr1lNyoU0Rn5r6v5GHe Nwq7DTeZlKoVji5GXki53mGrwENXr00m+xfc9ACMoWr5IM6McQUPXlQAQ/50fIGs lzXMZH/4EdPIVkkpCi+y8FLYw02oQg61U9G0HW02lQJy4Y4mudtvQFGzJ7f3SIZ3 EkKn5YLG0bqszq/amFNLQXlbnq3yI5zfcMHhHx0KuDsm2yNhrNA+AJP8tLI3JlxL +0YIA+fWuxQzz8Zu9+ckc8VAV83HIgQpXVzI6rQxdSwbmRgUu9ITO09ZmxaDHZF6 sDI6K3VouyaHJVkvu4coDajpYTjHLE26c9LAlaVBpgdnmnYy4vlndEqbfaBqOouX n0N2wJ3IGouIw7AnB9dTaZhM/Uo09hZKDr6kCm3hLfPn2+vi3yxsbwVwLaOpH3G3 kQ5ZFKjoA7XWOaXGOUMcmhByXkSxja+pSBppB58vJAFyVp73HYIpea3/q1Zd8S4S noJoqxDtD2zf26bDBIe83pUEnSnL8fAcsh3rlQP8HrWYhU7ZulVSE1ZvPkPgDpkY LVCPautTElsMp2Mg4a2oODGvSDN4/5h2dp6TaK4Qep92HHFOwPZQBQW607VwWR5N II8dB/l8PluKkgZ3ymhP1p9JAAZFe9a2cMmegRIiM74PkPty0kk= =guIi -----END PGP SIGNATURE----- Merge tag 'pull-or1k-20241203' of https://github.com/stffrdhrn/qemu into staging OpenRISC updates for 9.2.0 This series has 2 fixes: - Fix to keep serial@90000000 as default - Fixed undercounting of TTCR in continuous mode # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmdO56EACgkQw7McLV5m # J+T8BRAAxZMH4ykdRJBmYiFVOsYKagcdT6GGBHL44FGeQSr1lNyoU0Rn5r6v5GHe # Nwq7DTeZlKoVji5GXki53mGrwENXr00m+xfc9ACMoWr5IM6McQUPXlQAQ/50fIGs # lzXMZH/4EdPIVkkpCi+y8FLYw02oQg61U9G0HW02lQJy4Y4mudtvQFGzJ7f3SIZ3 # EkKn5YLG0bqszq/amFNLQXlbnq3yI5zfcMHhHx0KuDsm2yNhrNA+AJP8tLI3JlxL # +0YIA+fWuxQzz8Zu9+ckc8VAV83HIgQpXVzI6rQxdSwbmRgUu9ITO09ZmxaDHZF6 # sDI6K3VouyaHJVkvu4coDajpYTjHLE26c9LAlaVBpgdnmnYy4vlndEqbfaBqOouX # n0N2wJ3IGouIw7AnB9dTaZhM/Uo09hZKDr6kCm3hLfPn2+vi3yxsbwVwLaOpH3G3 # kQ5ZFKjoA7XWOaXGOUMcmhByXkSxja+pSBppB58vJAFyVp73HYIpea3/q1Zd8S4S # noJoqxDtD2zf26bDBIe83pUEnSnL8fAcsh3rlQP8HrWYhU7ZulVSE1ZvPkPgDpkY # LVCPautTElsMp2Mg4a2oODGvSDN4/5h2dp6TaK4Qep92HHFOwPZQBQW607VwWR5N # II8dB/l8PluKkgZ3ymhP1p9JAAZFe9a2cMmegRIiM74PkPty0kk= # =guIi # -----END PGP SIGNATURE----- # gpg: Signature made Tue 03 Dec 2024 11:12:33 GMT # gpg: using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * tag 'pull-or1k-20241203' of https://github.com/stffrdhrn/qemu: hw/openrisc: Fixed undercounting of TTCR in continuous mode hw/openrisc/openrisc_sim: keep serial@90000000 as default Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b733701533
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@ -29,7 +29,8 @@
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/* Tick Timer global state to allow all cores to be in sync */
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typedef struct OR1KTimerState {
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uint32_t ttcr;
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uint64_t last_clk;
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uint32_t ttcr_offset;
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uint64_t clk_offset;
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} OR1KTimerState;
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static OR1KTimerState *or1k_timer;
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@ -37,6 +38,8 @@ static OR1KTimerState *or1k_timer;
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void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val)
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{
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or1k_timer->ttcr = val;
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or1k_timer->ttcr_offset = val;
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or1k_timer->clk_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)
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@ -53,9 +56,8 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu)
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return;
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}
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk)
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/ TIMER_PERIOD);
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or1k_timer->last_clk = now;
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or1k_timer->ttcr = or1k_timer->ttcr_offset +
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DIV_ROUND_UP(now - or1k_timer->clk_offset, TIMER_PERIOD);
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}
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/* Update the next timeout time as difference between ttmr and ttcr */
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@ -69,7 +71,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
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}
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cpu_openrisc_count_update(cpu);
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now = or1k_timer->last_clk;
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) {
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wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1;
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@ -110,7 +112,8 @@ static void openrisc_timer_cb(void *opaque)
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case TIMER_NONE:
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break;
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case TIMER_INTR:
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or1k_timer->ttcr = 0;
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/* Zero the count by applying a negative offset to the counter */
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or1k_timer->ttcr_offset -= (cpu->env.ttmr & TTMR_TP);
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break;
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case TIMER_SHOT:
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cpu_openrisc_count_stop(cpu);
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@ -137,17 +140,18 @@ static void openrisc_count_reset(void *opaque)
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/* Reset the global timer state. */
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static void openrisc_timer_reset(void *opaque)
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{
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or1k_timer->ttcr = 0x00000000;
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or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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OpenRISCCPU *cpu = opaque;
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cpu_openrisc_count_set(cpu, 0);
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}
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static const VMStateDescription vmstate_or1k_timer = {
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.name = "or1k_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(ttcr, OR1KTimerState),
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VMSTATE_UINT64(last_clk, OR1KTimerState),
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VMSTATE_UINT32(ttcr_offset, OR1KTimerState),
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VMSTATE_UINT64(clk_offset, OR1KTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -250,7 +250,7 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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void *fdt = state->fdt;
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char *nodename;
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qemu_irq serial_irq;
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char alias[sizeof("uart0")];
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char alias[sizeof("serial0")];
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int i;
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if (num_cpus > 1) {
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@ -265,7 +265,7 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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serial_irq = get_cpu_irq(cpus, 0, irq_pin);
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}
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serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
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serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
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serial_hd(uart_idx),
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DEVICE_NATIVE_ENDIAN);
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/* Add device tree node for serial. */
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@ -277,10 +277,13 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);
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qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
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/* The /chosen node is created during fdt creation. */
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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snprintf(alias, sizeof(alias), "uart%d", uart_idx);
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if (uart_idx == 0) {
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/* The /chosen node is created during fdt creation. */
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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}
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snprintf(alias, sizeof(alias), "serial%d", uart_idx);
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qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
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g_free(nodename);
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}
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@ -326,11 +329,22 @@ static void openrisc_sim_init(MachineState *machine)
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smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
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}
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for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
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/*
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* We create the UART nodes starting with the highest address and
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* working downwards, because in QEMU the DTB nodes end up in the
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* DTB in reverse order of creation. Correctly-written guest software
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* will not care about the node order (it will look at stdout-path
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* or the alias nodes), but for the benefit of guest software which
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* just looks for the first UART node in the DTB, make sure the
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* lowest-address UART (which is QEMU's first serial port) appears
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* first in the DTB.
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*/
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for (n = OR1KSIM_UART_COUNT - 1; n >= 0; n--) {
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openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
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or1ksim_memmap[OR1KSIM_UART].size * n,
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or1ksim_memmap[OR1KSIM_UART].size,
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smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
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}
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load_addr = openrisc_load_kernel(ram_size, kernel_filename,
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&boot_info.bootstrap_pc);
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