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hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524 

The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model
it that way in hw/arm/armsse.c (along with the associated MPCs).  We
incorrectly also added an entry to the RAMInfo array for the AN524 in
hw/arm/mps2-tz.c, which was pointless because the CPU would never see
it.  Delete it.

The bug had no guest-visible effect because devices in the SSE-200
take priority over those in the board model (armsse.c maps
s->board_memory at priority -2).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-05-10 20:08:39 +01:00
parent 382c7160d1
commit b6889c5ae3
1 changed files with 1 additions and 7 deletions
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8
hw/arm/mps2-tz.c
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@ -243,19 +243,13 @@ static const RAMInfo an524_raminfo[] = { {
.size = 512 * KiB,
.mpc = 0,
.mrindex = 0,
}, {
.name = "sram",
.base = 0x20000000,
.size = 32 * 4 * KiB,
.mpc = -1,
.mrindex = 1,
}, {
/* We don't model QSPI flash yet; for now expose it as simple ROM */
.name = "QSPI",
.base = 0x28000000,
.size = 8 * MiB,
.mpc = 1,
.mrindex = 2,
.mrindex = 1,
.flags = IS_ROM,
}, {
.name = "DDR",