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target/riscv: Don't save pc when exception return 

As pc will be written by the xepc in exception return, just ignore
pc in translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:29 +08:00 committed by Alistair Francis
parent 79f26b3b95
commit b655dc7cd9
3 changed files with 6 additions and 9 deletions
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4
target/riscv/helper.h
View File

@ -100,8 +100,8 @@ DEF_HELPER_2(csrr_i128, tl, env, int)
DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_1(sret, tl, env)
DEF_HELPER_2(mret, tl, env, tl) DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush, void, env)
#endif #endif

7
target/riscv/insn_trans/trans_privileged.c.inc
View File

@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
if (has_ext(ctx, RVS)) { if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc); gen_helper_sret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */ tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} else { } else {
@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
static bool trans_mret(DisasContext *ctx, arg_mret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); gen_helper_mret(cpu_pc, cpu_env);
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
tcg_gen_exit_tb(NULL, 0); /* no chaining */ tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return true; return true;

4
target/riscv/op_helper.c
View File

@ -115,7 +115,7 @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) target_ulong helper_sret(CPURISCVState *env)
{ {
uint64_t mstatus; uint64_t mstatus;
target_ulong prev_priv, prev_virt; target_ulong prev_priv, prev_virt;
@ -176,7 +176,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
return retpc; return retpc;
} }
target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) target_ulong helper_mret(CPURISCVState *env)
{ {
if (!(env->priv >= PRV_M)) { if (!(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());