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target-tricore: Add missing 1.6 insn of BOL opcode format 

Some of the 1.6 ISA instructions were still missing. So let's add them.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann 2014-12-05 14:37:17 +00:00
parent e2bed107c6
commit b5fd8fa345
2 changed files with 54 additions and 1 deletions
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49
target-tricore/translate.c
View File

@ -3344,8 +3344,49 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
case OPC1_32_BOL_ST_W_LONGOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
break;
case OPC1_32_BOL_LD_B_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
/* raise illegal opcode trap */
}
break;
case OPC1_32_BOL_LD_BU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
} else {
/* raise illegal opcode trap */
}
break;
case OPC1_32_BOL_LD_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
/* raise illegal opcode trap */
}
break;
case OPC1_32_BOL_LD_HU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
} else {
/* raise illegal opcode trap */
}
break;
case OPC1_32_BOL_ST_B_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
/* raise illegal opcode trap */
}
break;
case OPC1_32_BOL_ST_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
/* raise illegal opcode trap */
}
break;
}
}
/* RC format */
@ -4679,6 +4720,12 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
case OPC1_32_BOL_LEA_LONGOFF:
case OPC1_32_BOL_ST_W_LONGOFF:
case OPC1_32_BOL_ST_A_LONGOFF:
case OPC1_32_BOL_LD_B_LONGOFF:
case OPC1_32_BOL_LD_BU_LONGOFF:
case OPC1_32_BOL_LD_H_LONGOFF:
case OPC1_32_BOL_LD_HU_LONGOFF:
case OPC1_32_BOL_ST_B_LONGOFF:
case OPC1_32_BOL_ST_H_LONGOFF:
decode_bol_opc(env, ctx, op1);
break;
/* BRC Format */

6
target-tricore/tricore-opcodes.h
View File

@ -451,6 +451,12 @@ enum {
OPC1_32_BOL_LEA_LONGOFF = 0xd9,
OPC1_32_BOL_ST_W_LONGOFF = 0x59,
OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
OPC1_32_BOL_LD_B_LONGOFF = 0x79, /* 1.6 only */
OPC1_32_BOL_LD_BU_LONGOFF = 0x39, /* 1.6 only */
OPC1_32_BOL_LD_H_LONGOFF = 0xc9, /* 1.6 only */
OPC1_32_BOL_LD_HU_LONGOFF = 0xb9, /* 1.6 only */
OPC1_32_BOL_ST_B_LONGOFF = 0xe9, /* 1.6 only */
OPC1_32_BOL_ST_H_LONGOFF = 0xf9, /* 1.6 only */
/* BRC Format */
OPCM_32_BRC_EQ_NEQ = 0xdf,
OPCM_32_BRC_GE = 0xff,