mirror of https://github.com/xemu-project/xemu.git
target/riscv: Compute mstatus.sd on demand
The position of this read-only field is dependent on the current xlen. Rather than having to compute that difference in many places, compute it only on read. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -185,10 +185,9 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
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void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
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void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
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{
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{
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uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
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uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
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uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
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MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
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MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
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MSTATUS64_UXL | sd;
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MSTATUS64_UXL;
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bool current_virt = riscv_cpu_virt_enabled(env);
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bool current_virt = riscv_cpu_virt_enabled(env);
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g_assert(riscv_has_ext(env, RVH));
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g_assert(riscv_has_ext(env, RVH));
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@ -477,10 +477,28 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
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}
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}
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/* Machine Trap Setup */
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/* Machine Trap Setup */
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/* We do not store SD explicitly, only compute it on demand. */
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static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
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{
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if ((status & MSTATUS_FS) == MSTATUS_FS ||
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(status & MSTATUS_XS) == MSTATUS_XS) {
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switch (xl) {
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case MXL_RV32:
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return status | MSTATUS32_SD;
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case MXL_RV64:
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return status | MSTATUS64_SD;
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default:
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g_assert_not_reached();
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}
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}
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return status;
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}
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static RISCVException read_mstatus(CPURISCVState *env, int csrno,
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static RISCVException read_mstatus(CPURISCVState *env, int csrno,
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target_ulong *val)
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target_ulong *val)
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{
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{
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*val = env->mstatus;
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*val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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@ -498,7 +516,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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{
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{
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uint64_t mstatus = env->mstatus;
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uint64_t mstatus = env->mstatus;
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uint64_t mask = 0;
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uint64_t mask = 0;
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int dirty;
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/* flush tlb on mstatus fields that affect VM */
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/* flush tlb on mstatus fields that affect VM */
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if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
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if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
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@ -520,12 +537,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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mstatus = (mstatus & ~mask) | (val & mask);
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mstatus = (mstatus & ~mask) | (val & mask);
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dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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((mstatus & MSTATUS_XS) == MSTATUS_XS);
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
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} else {
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mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
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/* SXL and UXL fields are for now read only */
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/* SXL and UXL fields are for now read only */
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mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
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mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
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mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
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mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
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@ -798,13 +810,8 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
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{
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{
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target_ulong mask = (sstatus_v1_10_mask);
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target_ulong mask = (sstatus_v1_10_mask);
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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/* TODO: Use SXL not MXL. */
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mask |= SSTATUS32_SD;
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*val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
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} else {
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mask |= SSTATUS64_SD;
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}
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*val = env->mstatus & mask;
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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@ -280,7 +280,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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static void mark_fs_dirty(DisasContext *ctx)
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static void mark_fs_dirty(DisasContext *ctx)
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{
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{
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TCGv tmp;
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TCGv tmp;
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target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
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if (ctx->mstatus_fs != MSTATUS_FS) {
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if (ctx->mstatus_fs != MSTATUS_FS) {
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/* Remember the state change for the rest of the TB. */
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/* Remember the state change for the rest of the TB. */
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@ -288,7 +287,7 @@ static void mark_fs_dirty(DisasContext *ctx)
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tmp = tcg_temp_new();
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tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_temp_free(tmp);
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tcg_temp_free(tmp);
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}
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}
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@ -299,7 +298,7 @@ static void mark_fs_dirty(DisasContext *ctx)
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tmp = tcg_temp_new();
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tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_temp_free(tmp);
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tcg_temp_free(tmp);
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}
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}
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