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hvf: Introduce hvf vcpu struct 

We will need more than a single field for hvf going forward. To keep
the global vcpu struct uncluttered, let's allocate a special hvf vcpu
struct, similar to how hax does it.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-12-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alexander Graf 2021-06-03 14:09:34 +01:00 committed by Peter Maydell
parent d662ede2b1
commit b533450e74
11 changed files with 248 additions and 237 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
accel/hvf/hvf-accel-ops.c
View File

@ -363,16 +363,20 @@ type_init(hvf_type_init);
static void hvf_vcpu_destroy(CPUState *cpu) static void hvf_vcpu_destroy(CPUState *cpu)
{ {
hv_return_t ret = hv_vcpu_destroy(cpu->hvf_fd); hv_return_t ret = hv_vcpu_destroy(cpu->hvf->fd);
assert_hvf_ok(ret); assert_hvf_ok(ret);
hvf_arch_vcpu_destroy(cpu); hvf_arch_vcpu_destroy(cpu);
g_free(cpu->hvf);
cpu->hvf = NULL;
} }
static int hvf_init_vcpu(CPUState *cpu) static int hvf_init_vcpu(CPUState *cpu)
{ {
int r; int r;
cpu->hvf = g_malloc0(sizeof(*cpu->hvf));
/* init cpu signals */ /* init cpu signals */
sigset_t set; sigset_t set;
struct sigaction sigact; struct sigaction sigact;
@ -384,7 +388,7 @@ static int hvf_init_vcpu(CPUState *cpu)
pthread_sigmask(SIG_BLOCK, NULL, &set); pthread_sigmask(SIG_BLOCK, NULL, &set);
sigdelset(&set, SIG_IPI); sigdelset(&set, SIG_IPI);
r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT);
cpu->vcpu_dirty = 1; cpu->vcpu_dirty = 1;
assert_hvf_ok(r); assert_hvf_ok(r);

3
include/hw/core/cpu.h
View File

@ -214,6 +214,7 @@ struct KVMState;
struct kvm_run; struct kvm_run;
struct hax_vcpu_state; struct hax_vcpu_state;
struct hvf_vcpu_state;
#define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_BITS 12
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
@ -406,7 +407,7 @@ struct CPUState {
struct hax_vcpu_state *hax_vcpu; struct hax_vcpu_state *hax_vcpu;
int hvf_fd; struct hvf_vcpu_state *hvf;
/* track IOMMUs whose translations we've cached in the TCG TLB */ /* track IOMMUs whose translations we've cached in the TCG TLB */
GArray *iommu_notifiers; GArray *iommu_notifiers;

4
include/sysemu/hvf_int.h
View File

@ -43,6 +43,10 @@ struct HVFState {
}; };
extern HVFState *hvf_state; extern HVFState *hvf_state;
struct hvf_vcpu_state {
int fd;
};
void assert_hvf_ok(hv_return_t ret); void assert_hvf_ok(hv_return_t ret);
int hvf_arch_init_vcpu(CPUState *cpu); int hvf_arch_init_vcpu(CPUState *cpu);
void hvf_arch_vcpu_destroy(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu);

104
target/i386/hvf/hvf.c
View File

@ -80,11 +80,11 @@ void vmx_update_tpr(CPUState *cpu)
int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
wreg(cpu->hvf_fd, HV_X86_TPR, tpr); wreg(cpu->hvf->fd, HV_X86_TPR, tpr);
if (irr == -1) { if (irr == -1) {
wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0); wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);
} else { } else {
wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :
irr >> 4); irr >> 4);
} }
} }
@ -92,7 +92,7 @@ void vmx_update_tpr(CPUState *cpu)
static void update_apic_tpr(CPUState *cpu) static void update_apic_tpr(CPUState *cpu)
{ {
X86CPU *x86_cpu = X86_CPU(cpu); X86CPU *x86_cpu = X86_CPU(cpu);
int tpr = rreg(cpu->hvf_fd, HV_X86_TPR) >> 4; int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4;
cpu_set_apic_tpr(x86_cpu->apic_state, tpr); cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
} }
@ -244,43 +244,43 @@ int hvf_arch_init_vcpu(CPUState *cpu)
} }
/* set VMCS control fields */ /* set VMCS control fields */
wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS,
cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,
VMCS_PIN_BASED_CTLS_EXTINT | VMCS_PIN_BASED_CTLS_EXTINT |
VMCS_PIN_BASED_CTLS_NMI | VMCS_PIN_BASED_CTLS_NMI |
VMCS_PIN_BASED_CTLS_VNMI)); VMCS_PIN_BASED_CTLS_VNMI));
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS,
cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
VMCS_PRI_PROC_BASED_CTLS_HLT | VMCS_PRI_PROC_BASED_CTLS_HLT |
VMCS_PRI_PROC_BASED_CTLS_MWAIT | VMCS_PRI_PROC_BASED_CTLS_MWAIT |
VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS, wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS,
cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,
VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES)); VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
0)); 0));
wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0); wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);
x86cpu = X86_CPU(cpu); x86cpu = X86_CPU(cpu);
x86cpu->env.xsave_buf = qemu_memalign(4096, 4096); x86cpu->env.xsave_buf = qemu_memalign(4096, 4096);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1); hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1);
return 0; return 0;
} }
@ -321,16 +321,16 @@ static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_in
} }
if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) {
env->has_error_code = true; env->has_error_code = true;
env->error_code = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERROR); env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR);
} }
} }
if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &
VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {
env->hflags2 |= HF2_NMI_MASK; env->hflags2 |= HF2_NMI_MASK;
} else { } else {
env->hflags2 &= ~HF2_NMI_MASK; env->hflags2 &= ~HF2_NMI_MASK;
} }
if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &
(VMCS_INTERRUPTIBILITY_STI_BLOCKING | (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
env->hflags |= HF_INHIBIT_IRQ_MASK; env->hflags |= HF_INHIBIT_IRQ_MASK;
@ -409,20 +409,20 @@ int hvf_vcpu_exec(CPUState *cpu)
return EXCP_HLT; return EXCP_HLT;
} }
hv_return_t r = hv_vcpu_run(cpu->hvf_fd); hv_return_t r = hv_vcpu_run(cpu->hvf->fd);
assert_hvf_ok(r); assert_hvf_ok(r);
/* handle VMEXIT */ /* handle VMEXIT */
uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON); uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON);
uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION); uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION);
uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd, uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd,
VMCS_EXIT_INSTRUCTION_LENGTH); VMCS_EXIT_INSTRUCTION_LENGTH);
uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO); uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);
hvf_store_events(cpu, ins_len, idtvec_info); hvf_store_events(cpu, ins_len, idtvec_info);
rip = rreg(cpu->hvf_fd, HV_X86_RIP); rip = rreg(cpu->hvf->fd, HV_X86_RIP);
env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS); env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);
qemu_mutex_lock_iothread(); qemu_mutex_lock_iothread();
@ -452,7 +452,7 @@ int hvf_vcpu_exec(CPUState *cpu)
case EXIT_REASON_EPT_FAULT: case EXIT_REASON_EPT_FAULT:
{ {
hvf_slot *slot; hvf_slot *slot;
uint64_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS); uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS);
if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) &&
((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) {
@ -497,7 +497,7 @@ int hvf_vcpu_exec(CPUState *cpu)
store_regs(cpu); store_regs(cpu);
break; break;
} else if (!string && !in) { } else if (!string && !in) {
RAX(env) = rreg(cpu->hvf_fd, HV_X86_RAX); RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX);
hvf_handle_io(env, port, &RAX(env), 1, size, 1); hvf_handle_io(env, port, &RAX(env), 1, size, 1);
macvm_set_rip(cpu, rip + ins_len); macvm_set_rip(cpu, rip + ins_len);
break; break;
@ -513,21 +513,21 @@ int hvf_vcpu_exec(CPUState *cpu)
break; break;
} }
case EXIT_REASON_CPUID: { case EXIT_REASON_CPUID: {
uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX); uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);
uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX); uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX);
uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX); uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);
uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX); uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);
if (rax == 1) { if (rax == 1) {
/* CPUID1.ecx.OSXSAVE needs to know CR4 */ /* CPUID1.ecx.OSXSAVE needs to know CR4 */
env->cr[4] = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4); env->cr[4] = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4);
} }
hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);
wreg(cpu->hvf_fd, HV_X86_RAX, rax); wreg(cpu->hvf->fd, HV_X86_RAX, rax);
wreg(cpu->hvf_fd, HV_X86_RBX, rbx); wreg(cpu->hvf->fd, HV_X86_RBX, rbx);
wreg(cpu->hvf_fd, HV_X86_RCX, rcx); wreg(cpu->hvf->fd, HV_X86_RCX, rcx);
wreg(cpu->hvf_fd, HV_X86_RDX, rdx); wreg(cpu->hvf->fd, HV_X86_RDX, rdx);
macvm_set_rip(cpu, rip + ins_len); macvm_set_rip(cpu, rip + ins_len);
break; break;
@ -535,16 +535,16 @@ int hvf_vcpu_exec(CPUState *cpu)
case EXIT_REASON_XSETBV: { case EXIT_REASON_XSETBV: {
X86CPU *x86_cpu = X86_CPU(cpu); X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX); uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);
uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX); uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);
uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX); uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);
if (ecx) { if (ecx) {
macvm_set_rip(cpu, rip + ins_len); macvm_set_rip(cpu, rip + ins_len);
break; break;
} }
env->xcr0 = ((uint64_t)edx << 32) | eax; env->xcr0 = ((uint64_t)edx << 32) | eax;
wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1); wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1);
macvm_set_rip(cpu, rip + ins_len); macvm_set_rip(cpu, rip + ins_len);
break; break;
} }
@ -583,11 +583,11 @@ int hvf_vcpu_exec(CPUState *cpu)
switch (cr) { switch (cr) {
case 0x0: { case 0x0: {
macvm_set_cr0(cpu->hvf_fd, RRX(env, reg)); macvm_set_cr0(cpu->hvf->fd, RRX(env, reg));
break; break;
} }
case 4: { case 4: {
macvm_set_cr4(cpu->hvf_fd, RRX(env, reg)); macvm_set_cr4(cpu->hvf->fd, RRX(env, reg));
break; break;
} }
case 8: { case 8: {
@ -623,7 +623,7 @@ int hvf_vcpu_exec(CPUState *cpu)
break; break;
} }
case EXIT_REASON_TASK_SWITCH: { case EXIT_REASON_TASK_SWITCH: {
uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO); uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);
x68_segment_selector sel = {.sel = exit_qual & 0xffff}; x68_segment_selector sel = {.sel = exit_qual & 0xffff};
vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo
@ -636,8 +636,8 @@ int hvf_vcpu_exec(CPUState *cpu)
break; break;
} }
case EXIT_REASON_RDPMC: case EXIT_REASON_RDPMC:
wreg(cpu->hvf_fd, HV_X86_RAX, 0); wreg(cpu->hvf->fd, HV_X86_RAX, 0);
wreg(cpu->hvf_fd, HV_X86_RDX, 0); wreg(cpu->hvf->fd, HV_X86_RDX, 0);
macvm_set_rip(cpu, rip + ins_len); macvm_set_rip(cpu, rip + ins_len);
break; break;
case VMX_REASON_VMCALL: case VMX_REASON_VMCALL:

24
target/i386/hvf/vmx.h
View File

@ -30,6 +30,8 @@
#include "vmcs.h" #include "vmcs.h"
#include "cpu.h" #include "cpu.h"
#include "x86.h" #include "x86.h"
#include "sysemu/hvf.h"
#include "sysemu/hvf_int.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
@ -179,15 +181,15 @@ static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)
uint64_t val; uint64_t val;
/* BUG, should take considering overlap.. */ /* BUG, should take considering overlap.. */
wreg(cpu->hvf_fd, HV_X86_RIP, rip); wreg(cpu->hvf->fd, HV_X86_RIP, rip);
env->eip = rip; env->eip = rip;
/* after moving forward in rip, we need to clean INTERRUPTABILITY */ /* after moving forward in rip, we need to clean INTERRUPTABILITY */
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); val = rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);
if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
env->hflags &= ~HF_INHIBIT_IRQ_MASK; env->hflags &= ~HF_INHIBIT_IRQ_MASK;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY,
val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
} }
@ -199,9 +201,9 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu)
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
env->hflags2 &= ~HF2_NMI_MASK; env->hflags2 &= ~HF2_NMI_MASK;
uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); uint32_t gi = (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);
gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
} }
static inline void vmx_set_nmi_blocking(CPUState *cpu) static inline void vmx_set_nmi_blocking(CPUState *cpu)
@ -210,16 +212,16 @@ static inline void vmx_set_nmi_blocking(CPUState *cpu)
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
env->hflags2 |= HF2_NMI_MASK; env->hflags2 |= HF2_NMI_MASK;
uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); uint32_t gi = (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);
gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING; gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
} }
static inline void vmx_set_nmi_window_exiting(CPUState *cpu) static inline void vmx_set_nmi_window_exiting(CPUState *cpu)
{ {
uint64_t val; uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val |
VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
} }
@ -228,8 +230,8 @@ static inline void vmx_clear_nmi_window_exiting(CPUState *cpu)
{ {
uint64_t val; uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val &
~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
} }

28
target/i386/hvf/x86.c
View File

@ -62,11 +62,11 @@ bool x86_read_segment_descriptor(struct CPUState *cpu,
} }
if (GDT_SEL == sel.ti) { if (GDT_SEL == sel.ti) {
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE); base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE);
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT); limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
} else { } else {
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE); base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE);
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT); limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT);
} }
if (sel.index * 8 >= limit) { if (sel.index * 8 >= limit) {
@ -85,11 +85,11 @@ bool x86_write_segment_descriptor(struct CPUState *cpu,
uint32_t limit; uint32_t limit;
if (GDT_SEL == sel.ti) { if (GDT_SEL == sel.ti) {
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE); base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE);
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT); limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
} else { } else {
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE); base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE);
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT); limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT);
} }
if (sel.index * 8 >= limit) { if (sel.index * 8 >= limit) {
@ -103,8 +103,8 @@ bool x86_write_segment_descriptor(struct CPUState *cpu,
bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
int gate) int gate)
{ {
target_ulong base = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE); target_ulong base = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE);
uint32_t limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT); uint32_t limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT);
memset(idt_desc, 0, sizeof(*idt_desc)); memset(idt_desc, 0, sizeof(*idt_desc));
if (gate * 8 >= limit) { if (gate * 8 >= limit) {
@ -118,7 +118,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
bool x86_is_protected(struct CPUState *cpu) bool x86_is_protected(struct CPUState *cpu)
{ {
uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);
return cr0 & CR0_PE; return cr0 & CR0_PE;
} }
@ -136,7 +136,7 @@ bool x86_is_v8086(struct CPUState *cpu)
bool x86_is_long_mode(struct CPUState *cpu) bool x86_is_long_mode(struct CPUState *cpu)
{ {
return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA;
} }
bool x86_is_long64_mode(struct CPUState *cpu) bool x86_is_long64_mode(struct CPUState *cpu)
@ -149,13 +149,13 @@ bool x86_is_long64_mode(struct CPUState *cpu)
bool x86_is_paging_mode(struct CPUState *cpu) bool x86_is_paging_mode(struct CPUState *cpu)
{ {
uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);
return cr0 & CR0_PG; return cr0 & CR0_PG;
} }
bool x86_is_pae_enabled(struct CPUState *cpu) bool x86_is_pae_enabled(struct CPUState *cpu)
{ {
uint64_t cr4 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4); uint64_t cr4 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4);
return cr4 & CR4_PAE; return cr4 & CR4_PAE;
} }

26
target/i386/hvf/x86_descr.c
View File

@ -48,47 +48,47 @@ static const struct vmx_segment_field {
uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg) uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg)
{ {
return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit);
} }
uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg) uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg)
{ {
return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes);
} }
uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg) uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg)
{ {
return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base);
} }
x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg)
{ {
x68_segment_selector sel; x68_segment_selector sel;
sel.sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); sel.sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector);
return sel; return sel;
} }
void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg) void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg)
{ {
wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel); wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel);
} }
void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg) void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg)
{ {
desc->sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); desc->sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector);
desc->base = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); desc->base = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base);
desc->limit = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); desc->limit = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit);
desc->ar = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); desc->ar = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes);
} }
void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg) void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg)
{ {
const struct vmx_segment_field *sf = &vmx_segment_fields[seg]; const struct vmx_segment_field *sf = &vmx_segment_fields[seg];
wvmcs(cpu->hvf_fd, sf->base, desc->base); wvmcs(cpu->hvf->fd, sf->base, desc->base);
wvmcs(cpu->hvf_fd, sf->limit, desc->limit); wvmcs(cpu->hvf->fd, sf->limit, desc->limit);
wvmcs(cpu->hvf_fd, sf->selector, desc->sel); wvmcs(cpu->hvf->fd, sf->selector, desc->sel);
wvmcs(cpu->hvf_fd, sf->ar_bytes, desc->ar); wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar);
} }
void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc) void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)

62
target/i386/hvf/x86_emu.c
View File

@ -674,7 +674,7 @@ void simulate_rdmsr(struct CPUState *cpu)
switch (msr) { switch (msr) {
case MSR_IA32_TSC: case MSR_IA32_TSC:
val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET); val = rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET);
break; break;
case MSR_IA32_APICBASE: case MSR_IA32_APICBASE:
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
@ -683,16 +683,16 @@ void simulate_rdmsr(struct CPUState *cpu)
val = x86_cpu->ucode_rev; val = x86_cpu->ucode_rev;
break; break;
case MSR_EFER: case MSR_EFER:
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER); val = rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER);
break; break;
case MSR_FSBASE: case MSR_FSBASE:
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE); val = rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE);
break; break;
case MSR_GSBASE: case MSR_GSBASE:
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE); val = rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE);
break; break;
case MSR_KERNELGSBASE: case MSR_KERNELGSBASE:
val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE); val = rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE);
break; break;
case MSR_STAR: case MSR_STAR:
abort(); abort();
@ -780,13 +780,13 @@ void simulate_wrmsr(struct CPUState *cpu)
cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
break; break;
case MSR_FSBASE: case MSR_FSBASE:
wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data); wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data);
break; break;
case MSR_GSBASE: case MSR_GSBASE:
wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data); wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data);
break; break;
case MSR_KERNELGSBASE: case MSR_KERNELGSBASE:
wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data); wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data);
break; break;
case MSR_STAR: case MSR_STAR:
abort(); abort();
@ -799,9 +799,9 @@ void simulate_wrmsr(struct CPUState *cpu)
break; break;
case MSR_EFER: case MSR_EFER:
/*printf("new efer %llx\n", EFER(cpu));*/ /*printf("new efer %llx\n", EFER(cpu));*/
wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data); wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data);
if (data & MSR_EFER_NXE) { if (data & MSR_EFER_NXE) {
hv_vcpu_invalidate_tlb(cpu->hvf_fd); hv_vcpu_invalidate_tlb(cpu->hvf->fd);
} }
break; break;
case MSR_MTRRphysBase(0): case MSR_MTRRphysBase(0):
@ -1425,21 +1425,21 @@ void load_regs(struct CPUState *cpu)
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
int i = 0; int i = 0;
RRX(env, R_EAX) = rreg(cpu->hvf_fd, HV_X86_RAX); RRX(env, R_EAX) = rreg(cpu->hvf->fd, HV_X86_RAX);
RRX(env, R_EBX) = rreg(cpu->hvf_fd, HV_X86_RBX); RRX(env, R_EBX) = rreg(cpu->hvf->fd, HV_X86_RBX);
RRX(env, R_ECX) = rreg(cpu->hvf_fd, HV_X86_RCX); RRX(env, R_ECX) = rreg(cpu->hvf->fd, HV_X86_RCX);
RRX(env, R_EDX) = rreg(cpu->hvf_fd, HV_X86_RDX); RRX(env, R_EDX) = rreg(cpu->hvf->fd, HV_X86_RDX);
RRX(env, R_ESI) = rreg(cpu->hvf_fd, HV_X86_RSI); RRX(env, R_ESI) = rreg(cpu->hvf->fd, HV_X86_RSI);
RRX(env, R_EDI) = rreg(cpu->hvf_fd, HV_X86_RDI); RRX(env, R_EDI) = rreg(cpu->hvf->fd, HV_X86_RDI);
RRX(env, R_ESP) = rreg(cpu->hvf_fd, HV_X86_RSP); RRX(env, R_ESP) = rreg(cpu->hvf->fd, HV_X86_RSP);
RRX(env, R_EBP) = rreg(cpu->hvf_fd, HV_X86_RBP); RRX(env, R_EBP) = rreg(cpu->hvf->fd, HV_X86_RBP);
for (i = 8; i < 16; i++) { for (i = 8; i < 16; i++) {
RRX(env, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i); RRX(env, i) = rreg(cpu->hvf->fd, HV_X86_RAX + i);
} }
env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS); env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);
rflags_to_lflags(env); rflags_to_lflags(env);
env->eip = rreg(cpu->hvf_fd, HV_X86_RIP); env->eip = rreg(cpu->hvf->fd, HV_X86_RIP);
} }
void store_regs(struct CPUState *cpu) void store_regs(struct CPUState *cpu)
@ -1448,20 +1448,20 @@ void store_regs(struct CPUState *cpu)
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
int i = 0; int i = 0;
wreg(cpu->hvf_fd, HV_X86_RAX, RAX(env)); wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env));
wreg(cpu->hvf_fd, HV_X86_RBX, RBX(env)); wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env));
wreg(cpu->hvf_fd, HV_X86_RCX, RCX(env)); wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env));
wreg(cpu->hvf_fd, HV_X86_RDX, RDX(env)); wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env));
wreg(cpu->hvf_fd, HV_X86_RSI, RSI(env)); wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env));
wreg(cpu->hvf_fd, HV_X86_RDI, RDI(env)); wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env));
wreg(cpu->hvf_fd, HV_X86_RBP, RBP(env)); wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env));
wreg(cpu->hvf_fd, HV_X86_RSP, RSP(env)); wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) { for (i = 8; i < 16; i++) {
wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(env, i)); wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i));
} }
lflags_to_rflags(env); lflags_to_rflags(env);
wreg(cpu->hvf_fd, HV_X86_RFLAGS, env->eflags); wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags);
macvm_set_rip(cpu, env->eip); macvm_set_rip(cpu, env->eip);
} }

4
target/i386/hvf/x86_mmu.c
View File

@ -127,7 +127,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
pt->err_code |= MMU_PAGE_PT; pt->err_code |= MMU_PAGE_PT;
} }
uint32_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); uint32_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);
/* check protection */ /* check protection */
if (cr0 & CR0_WP) { if (cr0 & CR0_WP) {
if (pt->write_access && !pte_write_access(pte)) { if (pt->write_access && !pte_write_access(pte)) {
@ -172,7 +172,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code,
{ {
int top_level, level; int top_level, level;
bool is_large = false; bool is_large = false;
target_ulong cr3 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3); target_ulong cr3 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3);
uint64_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; uint64_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
memset(pt, 0, sizeof(*pt)); memset(pt, 0, sizeof(*pt));

12
target/i386/hvf/x86_task.c
View File

@ -62,7 +62,7 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
X86CPU *x86_cpu = X86_CPU(cpu); X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &x86_cpu->env;
wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3); wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3);
env->eip = tss->eip; env->eip = tss->eip;
env->eflags = tss->eflags | 2; env->eflags = tss->eflags | 2;
@ -111,11 +111,11 @@ static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segme
void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type) void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
{ {
uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP); uint64_t rip = rreg(cpu->hvf->fd, HV_X86_RIP);
if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION && if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
gate_type != VMCS_INTR_T_HWINTR && gate_type != VMCS_INTR_T_HWINTR &&
gate_type != VMCS_INTR_T_NMI)) { gate_type != VMCS_INTR_T_NMI)) {
int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH); int ins_len = rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH);
macvm_set_rip(cpu, rip + ins_len); macvm_set_rip(cpu, rip + ins_len);
return; return;
} }
@ -174,12 +174,12 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea
//ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc); //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
VM_PANIC("task_switch_16"); VM_PANIC("task_switch_16");
macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS); macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) | CR0_TS);
x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR);
store_regs(cpu); store_regs(cpu);
hv_vcpu_invalidate_tlb(cpu->hvf_fd); hv_vcpu_invalidate_tlb(cpu->hvf->fd);
hv_vcpu_flush(cpu->hvf_fd); hv_vcpu_flush(cpu->hvf->fd);
} }

210
target/i386/hvf/x86hvf.c
View File

@ -80,7 +80,7 @@ void hvf_put_xsave(CPUState *cpu_state)
x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave); x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave);
if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) { if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) {
abort(); abort();
} }
} }
@ -90,19 +90,19 @@ void hvf_put_segments(CPUState *cpu_state)
CPUX86State *env = &X86_CPU(cpu_state)->env; CPUX86State *env = &X86_CPU(cpu_state)->env;
struct vmx_segment seg; struct vmx_segment seg;
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base); wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
/* wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]); */ /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]); wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]);
vmx_update_tpr(cpu_state); vmx_update_tpr(cpu_state);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer); wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer);
macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]); macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]);
macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]); macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]);
hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);
vmx_write_segment_descriptor(cpu_state, &seg, R_CS); vmx_write_segment_descriptor(cpu_state, &seg, R_CS);
@ -128,31 +128,31 @@ void hvf_put_segments(CPUState *cpu_state)
hvf_set_segment(cpu_state, &seg, &env->ldt, false); hvf_set_segment(cpu_state, &seg, &env->ldt, false);
vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR);
hv_vcpu_flush(cpu_state->hvf_fd); hv_vcpu_flush(cpu_state->hvf->fd);
} }
void hvf_put_msrs(CPUState *cpu_state) void hvf_put_msrs(CPUState *cpu_state)
{ {
CPUX86State *env = &X86_CPU(cpu_state)->env; CPUX86State *env = &X86_CPU(cpu_state)->env;
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS,
env->sysenter_cs); env->sysenter_cs);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP,
env->sysenter_esp); env->sysenter_esp);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP,
env->sysenter_eip); env->sysenter_eip);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star);
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_CSTAR, env->cstar); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, env->kernelgsbase); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FMASK, env->fmask); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_LSTAR, env->lstar); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar);
#endif #endif
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base); hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base);
} }
@ -162,7 +162,7 @@ void hvf_get_xsave(CPUState *cpu_state)
xsave = X86_CPU(cpu_state)->env.xsave_buf; xsave = X86_CPU(cpu_state)->env.xsave_buf;
if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) { if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) {
abort(); abort();
} }
@ -201,17 +201,17 @@ void hvf_get_segments(CPUState *cpu_state)
vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR);
hvf_get_segment(&env->ldt, &seg); hvf_get_segment(&env->ldt, &seg);
env->idt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT); env->idt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT);
env->idt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE); env->idt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE);
env->gdt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT); env->gdt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
env->gdt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE); env->gdt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE);
env->cr[0] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR0); env->cr[0] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0);
env->cr[2] = 0; env->cr[2] = 0;
env->cr[3] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3); env->cr[3] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3);
env->cr[4] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4); env->cr[4] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4);
env->efer = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER); env->efer = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER);
} }
void hvf_get_msrs(CPUState *cpu_state) void hvf_get_msrs(CPUState *cpu_state)
@ -219,27 +219,27 @@ void hvf_get_msrs(CPUState *cpu_state)
CPUX86State *env = &X86_CPU(cpu_state)->env; CPUX86State *env = &X86_CPU(cpu_state)->env;
uint64_t tmp; uint64_t tmp;
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp);
env->sysenter_cs = tmp; env->sysenter_cs = tmp;
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp);
env->sysenter_esp = tmp; env->sysenter_esp = tmp;
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, &tmp); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp);
env->sysenter_eip = tmp; env->sysenter_eip = tmp;
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_STAR, &env->star); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star);
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_CSTAR, &env->cstar); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar);
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, &env->kernelgsbase); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase);
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_FMASK, &env->fmask); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask);
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_LSTAR, &env->lstar); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar);
#endif #endif
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp); hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp);
env->tsc = rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET); env->tsc = rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET);
} }
int hvf_put_registers(CPUState *cpu_state) int hvf_put_registers(CPUState *cpu_state)
@ -247,26 +247,26 @@ int hvf_put_registers(CPUState *cpu_state)
X86CPU *x86cpu = X86_CPU(cpu_state); X86CPU *x86cpu = X86_CPU(cpu_state);
CPUX86State *env = &x86cpu->env; CPUX86State *env = &x86cpu->env;
wreg(cpu_state->hvf_fd, HV_X86_RAX, env->regs[R_EAX]); wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]);
wreg(cpu_state->hvf_fd, HV_X86_RBX, env->regs[R_EBX]); wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]);
wreg(cpu_state->hvf_fd, HV_X86_RCX, env->regs[R_ECX]); wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]);
wreg(cpu_state->hvf_fd, HV_X86_RDX, env->regs[R_EDX]); wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]);
wreg(cpu_state->hvf_fd, HV_X86_RBP, env->regs[R_EBP]); wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]);
wreg(cpu_state->hvf_fd, HV_X86_RSP, env->regs[R_ESP]); wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]);
wreg(cpu_state->hvf_fd, HV_X86_RSI, env->regs[R_ESI]); wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]);
wreg(cpu_state->hvf_fd, HV_X86_RDI, env->regs[R_EDI]); wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]);
wreg(cpu_state->hvf_fd, HV_X86_R8, env->regs[8]); wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]);
wreg(cpu_state->hvf_fd, HV_X86_R9, env->regs[9]); wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]);
wreg(cpu_state->hvf_fd, HV_X86_R10, env->regs[10]); wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]);
wreg(cpu_state->hvf_fd, HV_X86_R11, env->regs[11]); wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]);
wreg(cpu_state->hvf_fd, HV_X86_R12, env->regs[12]); wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]);
wreg(cpu_state->hvf_fd, HV_X86_R13, env->regs[13]); wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]);
wreg(cpu_state->hvf_fd, HV_X86_R14, env->regs[14]); wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]);
wreg(cpu_state->hvf_fd, HV_X86_R15, env->regs[15]); wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]);
wreg(cpu_state->hvf_fd, HV_X86_RFLAGS, env->eflags); wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags);
wreg(cpu_state->hvf_fd, HV_X86_RIP, env->eip); wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip);
wreg(cpu_state->hvf_fd, HV_X86_XCR0, env->xcr0); wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0);
hvf_put_xsave(cpu_state); hvf_put_xsave(cpu_state);
@ -274,14 +274,14 @@ int hvf_put_registers(CPUState *cpu_state)
hvf_put_msrs(cpu_state); hvf_put_msrs(cpu_state);
wreg(cpu_state->hvf_fd, HV_X86_DR0, env->dr[0]); wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]);
wreg(cpu_state->hvf_fd, HV_X86_DR1, env->dr[1]); wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]);
wreg(cpu_state->hvf_fd, HV_X86_DR2, env->dr[2]); wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]);
wreg(cpu_state->hvf_fd, HV_X86_DR3, env->dr[3]); wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]);
wreg(cpu_state->hvf_fd, HV_X86_DR4, env->dr[4]); wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]);
wreg(cpu_state->hvf_fd, HV_X86_DR5, env->dr[5]); wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]);
wreg(cpu_state->hvf_fd, HV_X86_DR6, env->dr[6]); wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]);
wreg(cpu_state->hvf_fd, HV_X86_DR7, env->dr[7]); wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]);
return 0; return 0;
} }
@ -291,40 +291,40 @@ int hvf_get_registers(CPUState *cpu_state)
X86CPU *x86cpu = X86_CPU(cpu_state); X86CPU *x86cpu = X86_CPU(cpu_state);
CPUX86State *env = &x86cpu->env; CPUX86State *env = &x86cpu->env;
env->regs[R_EAX] = rreg(cpu_state->hvf_fd, HV_X86_RAX); env->regs[R_EAX] = rreg(cpu_state->hvf->fd, HV_X86_RAX);
env->regs[R_EBX] = rreg(cpu_state->hvf_fd, HV_X86_RBX); env->regs[R_EBX] = rreg(cpu_state->hvf->fd, HV_X86_RBX);
env->regs[R_ECX] = rreg(cpu_state->hvf_fd, HV_X86_RCX); env->regs[R_ECX] = rreg(cpu_state->hvf->fd, HV_X86_RCX);
env->regs[R_EDX] = rreg(cpu_state->hvf_fd, HV_X86_RDX); env->regs[R_EDX] = rreg(cpu_state->hvf->fd, HV_X86_RDX);
env->regs[R_EBP] = rreg(cpu_state->hvf_fd, HV_X86_RBP); env->regs[R_EBP] = rreg(cpu_state->hvf->fd, HV_X86_RBP);
env->regs[R_ESP] = rreg(cpu_state->hvf_fd, HV_X86_RSP); env->regs[R_ESP] = rreg(cpu_state->hvf->fd, HV_X86_RSP);
env->regs[R_ESI] = rreg(cpu_state->hvf_fd, HV_X86_RSI); env->regs[R_ESI] = rreg(cpu_state->hvf->fd, HV_X86_RSI);
env->regs[R_EDI] = rreg(cpu_state->hvf_fd, HV_X86_RDI); env->regs[R_EDI] = rreg(cpu_state->hvf->fd, HV_X86_RDI);
env->regs[8] = rreg(cpu_state->hvf_fd, HV_X86_R8); env->regs[8] = rreg(cpu_state->hvf->fd, HV_X86_R8);
env->regs[9] = rreg(cpu_state->hvf_fd, HV_X86_R9); env->regs[9] = rreg(cpu_state->hvf->fd, HV_X86_R9);
env->regs[10] = rreg(cpu_state->hvf_fd, HV_X86_R10); env->regs[10] = rreg(cpu_state->hvf->fd, HV_X86_R10);
env->regs[11] = rreg(cpu_state->hvf_fd, HV_X86_R11); env->regs[11] = rreg(cpu_state->hvf->fd, HV_X86_R11);
env->regs[12] = rreg(cpu_state->hvf_fd, HV_X86_R12); env->regs[12] = rreg(cpu_state->hvf->fd, HV_X86_R12);
env->regs[13] = rreg(cpu_state->hvf_fd, HV_X86_R13); env->regs[13] = rreg(cpu_state->hvf->fd, HV_X86_R13);
env->regs[14] = rreg(cpu_state->hvf_fd, HV_X86_R14); env->regs[14] = rreg(cpu_state->hvf->fd, HV_X86_R14);
env->regs[15] = rreg(cpu_state->hvf_fd, HV_X86_R15); env->regs[15] = rreg(cpu_state->hvf->fd, HV_X86_R15);
env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS);
env->eip = rreg(cpu_state->hvf_fd, HV_X86_RIP); env->eip = rreg(cpu_state->hvf->fd, HV_X86_RIP);
hvf_get_xsave(cpu_state); hvf_get_xsave(cpu_state);
env->xcr0 = rreg(cpu_state->hvf_fd, HV_X86_XCR0); env->xcr0 = rreg(cpu_state->hvf->fd, HV_X86_XCR0);
hvf_get_segments(cpu_state); hvf_get_segments(cpu_state);
hvf_get_msrs(cpu_state); hvf_get_msrs(cpu_state);
env->dr[0] = rreg(cpu_state->hvf_fd, HV_X86_DR0); env->dr[0] = rreg(cpu_state->hvf->fd, HV_X86_DR0);
env->dr[1] = rreg(cpu_state->hvf_fd, HV_X86_DR1); env->dr[1] = rreg(cpu_state->hvf->fd, HV_X86_DR1);
env->dr[2] = rreg(cpu_state->hvf_fd, HV_X86_DR2); env->dr[2] = rreg(cpu_state->hvf->fd, HV_X86_DR2);
env->dr[3] = rreg(cpu_state->hvf_fd, HV_X86_DR3); env->dr[3] = rreg(cpu_state->hvf->fd, HV_X86_DR3);
env->dr[4] = rreg(cpu_state->hvf_fd, HV_X86_DR4); env->dr[4] = rreg(cpu_state->hvf->fd, HV_X86_DR4);
env->dr[5] = rreg(cpu_state->hvf_fd, HV_X86_DR5); env->dr[5] = rreg(cpu_state->hvf->fd, HV_X86_DR5);
env->dr[6] = rreg(cpu_state->hvf_fd, HV_X86_DR6); env->dr[6] = rreg(cpu_state->hvf->fd, HV_X86_DR6);
env->dr[7] = rreg(cpu_state->hvf_fd, HV_X86_DR7); env->dr[7] = rreg(cpu_state->hvf->fd, HV_X86_DR7);
x86_update_hflags(env); x86_update_hflags(env);
return 0; return 0;
@ -333,16 +333,16 @@ int hvf_get_registers(CPUState *cpu_state)
static void vmx_set_int_window_exiting(CPUState *cpu) static void vmx_set_int_window_exiting(CPUState *cpu)
{ {
uint64_t val; uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val |
VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
} }
void vmx_clear_int_window_exiting(CPUState *cpu) void vmx_clear_int_window_exiting(CPUState *cpu)
{ {
uint64_t val; uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val &
~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
} }
@ -378,7 +378,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state)
uint64_t info = 0; uint64_t info = 0;
if (have_event) { if (have_event) {
info = vector | intr_type | VMCS_INTR_VALID; info = vector | intr_type | VMCS_INTR_VALID;
uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON); uint64_t reason = rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON);
if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) { if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) {
vmx_clear_nmi_blocking(cpu_state); vmx_clear_nmi_blocking(cpu_state);
} }
@ -387,17 +387,17 @@ bool hvf_inject_interrupts(CPUState *cpu_state)
info &= ~(1 << 12); /* clear undefined bit */ info &= ~(1 << 12); /* clear undefined bit */
if (intr_type == VMCS_INTR_T_SWINTR || if (intr_type == VMCS_INTR_T_SWINTR ||
intr_type == VMCS_INTR_T_SWEXCEPTION) { intr_type == VMCS_INTR_T_SWEXCEPTION) {
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);
} }
if (env->has_error_code) { if (env->has_error_code) {
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR,
env->error_code); env->error_code);
/* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */
info |= VMCS_INTR_DEL_ERRCODE; info |= VMCS_INTR_DEL_ERRCODE;
} }
/*printf("reinject %lx err %d\n", info, err);*/ /*printf("reinject %lx err %d\n", info, err);*/
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info);
}; };
} }
@ -405,7 +405,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state)
if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) {
cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI; cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI;
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info);
} else { } else {
vmx_set_nmi_window_exiting(cpu_state); vmx_set_nmi_window_exiting(cpu_state);
} }
@ -417,7 +417,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state)
int line = cpu_get_pic_interrupt(&x86cpu->env); int line = cpu_get_pic_interrupt(&x86cpu->env);
cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD; cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
if (line >= 0) { if (line >= 0) {
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line |
VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
} }
} }
@ -433,7 +433,7 @@ int hvf_process_events(CPUState *cpu_state)
X86CPU *cpu = X86_CPU(cpu_state); X86CPU *cpu = X86_CPU(cpu_state);
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS);
if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
cpu_synchronize_state(cpu_state); cpu_synchronize_state(cpu_state);