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Define Freescale cores specific MMU model, exceptions and input bus. 

(but do not provide any actual implementation).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-11-17 22:42:36 +00:00
parent 05332d70fd
commit b4095fed95
3 changed files with 109 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
target-ppc/cpu.h
View File

@ -104,8 +104,10 @@ enum powerpc_mmu_t {
POWERPC_MMU_SOFT_4xx, POWERPC_MMU_SOFT_4xx,
/* PowerPC 4xx MMU with software TLB and zones protections */ /* PowerPC 4xx MMU with software TLB and zones protections */
POWERPC_MMU_SOFT_4xx_Z, POWERPC_MMU_SOFT_4xx_Z,
/* PowerPC 4xx MMU in real mode only */ /* PowerPC MMU in real mode only */
POWERPC_MMU_REAL_4xx, POWERPC_MMU_REAL,
/* Freescale MPC8xx MMU model */
POWERPC_MMU_MPC8xx,
/* BookE MMU model */ /* BookE MMU model */
POWERPC_MMU_BOOKE, POWERPC_MMU_BOOKE,
/* BookE FSL MMU model */ /* BookE FSL MMU model */
@ -171,8 +173,8 @@ enum {
POWERPC_EXCP_DECR = 10, /* Decrementer exception */ POWERPC_EXCP_DECR = 10, /* Decrementer exception */
POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
POWERPC_EXCP_DTLB = 13, /* Data TLB error */ POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */ POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
/* Vectors 16 to 31 are reserved */ /* Vectors 16 to 31 are reserved */
POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
@ -201,21 +203,27 @@ enum {
/* 602 specific exceptions */ /* 602 specific exceptions */
POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
/* 602/603 specific exceptions */ /* 602/603 specific exceptions */
POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */ POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
/* Exceptions available on most PowerPC */ /* Exceptions available on most PowerPC */
POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */ POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
POWERPC_EXCP_SMI = 83, /* System management interrupt */ POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */ POWERPC_EXCP_SMI = 84, /* System management interrupt */
POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
/* 7xx/74xx specific exceptions */ /* 7xx/74xx specific exceptions */
POWERPC_EXCP_THERM = 85, /* Thermal interrupt */ POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
/* 74xx specific exceptions */ /* 74xx specific exceptions */
POWERPC_EXCP_VPUA = 86, /* Vector assist exception */ POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
/* 970FX specific exceptions */ /* 970FX specific exceptions */
POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */ POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
POWERPC_EXCP_MAINT = 88, /* Maintenance exception */ POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
/* Freescale embeded cores specific exceptions */
POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
/* EOL */ /* EOL */
POWERPC_EXCP_NB = 96, POWERPC_EXCP_NB = 96,
/* Qemu exceptions: used internally during code translation */ /* Qemu exceptions: used internally during code translation */
@ -280,6 +288,8 @@ enum powerpc_input_t {
PPC_FLAGS_INPUT_970, PPC_FLAGS_INPUT_970,
/* PowerPC 401 bus */ /* PowerPC 401 bus */
PPC_FLAGS_INPUT_401, PPC_FLAGS_INPUT_401,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
}; };
#define PPC_INPUT(env) (env->bus_model) #define PPC_INPUT(env) (env->bus_model)
@ -1259,6 +1269,22 @@ enum {
PPC40x_INPUT_NB, PPC40x_INPUT_NB,
}; };
enum {
/* RCPU input pins */
PPCRCPU_INPUT_PORESET = 0,
PPCRCPU_INPUT_HRESET = 1,
PPCRCPU_INPUT_SRESET = 2,
PPCRCPU_INPUT_IRQ0 = 3,
PPCRCPU_INPUT_IRQ1 = 4,
PPCRCPU_INPUT_IRQ2 = 5,
PPCRCPU_INPUT_IRQ3 = 6,
PPCRCPU_INPUT_IRQ4 = 7,
PPCRCPU_INPUT_IRQ5 = 8,
PPCRCPU_INPUT_IRQ6 = 9,
PPCRCPU_INPUT_IRQ7 = 10,
PPCRCPU_INPUT_NB,
};
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
enum { enum {
/* PowerPC 970 input pins */ /* PowerPC 970 input pins */

78
target-ppc/helper.c
View File

@ -1357,7 +1357,7 @@ static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx: case POWERPC_MMU_SOFT_74xx:
case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_REAL:
case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE:
ctx->prot |= PAGE_WRITE; ctx->prot |= PAGE_WRITE;
break; break;
@ -1392,6 +1392,10 @@ static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
} }
} }
break; break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "BookE FSL MMU model not implemented\n"); cpu_abort(env, "BookE FSL MMU model not implemented\n");
@ -1445,12 +1449,16 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
ret = mmubooke_get_physical_address(env, ctx, eaddr, ret = mmubooke_get_physical_address(env, ctx, eaddr,
rw, access_type); rw, access_type);
break; break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "BookE FSL MMU model not implemented\n"); cpu_abort(env, "BookE FSL MMU model not implemented\n");
return -1; return -1;
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC 401 does not do any translation\n"); cpu_abort(env, "PowerPC in real mode do not do any translation\n");
return -1; return -1;
default: default:
cpu_abort(env, "Unknown or invalid MMU model\n"); cpu_abort(env, "Unknown or invalid MMU model\n");
@ -1537,15 +1545,19 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
break; break;
case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE MMU model is not implemented\n");
return -1; return -1;
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE FSL MMU model is not implemented\n");
return -1; return -1;
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_MPC8xx:
cpu_abort(env, "PowerPC 401 should never raise any MMU " /* XXX: TODO */
"exceptions\n"); cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
return -1; return -1;
default: default:
cpu_abort(env, "Unknown or invalid MMU model\n"); cpu_abort(env, "Unknown or invalid MMU model\n");
@ -1632,17 +1644,21 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
else else
env->spr[SPR_DSISR] = 0x40000000; env->spr[SPR_DSISR] = 0x40000000;
break; break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE MMU model is not implemented\n");
return -1; return -1;
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE FSL MMU model is not implemented\n");
return -1; return -1;
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC 401 should never raise any MMU " cpu_abort(env, "PowerPC in real mode should never raise "
"exceptions\n"); "any MMU exceptions\n");
return -1; return -1;
default: default:
cpu_abort(env, "Unknown or invalid MMU model\n"); cpu_abort(env, "Unknown or invalid MMU model\n");
@ -1921,16 +1937,20 @@ void ppc_tlb_invalidate_all (CPUPPCState *env)
case POWERPC_MMU_SOFT_4xx_Z: case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_all(env); ppc4xx_tlb_invalidate_all(env);
break; break;
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_REAL:
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
break; break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE MMU model is not implemented\n");
break; break;
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE MMU model is not implemented\n");
break; break;
case POWERPC_MMU_32B: case POWERPC_MMU_32B:
case POWERPC_MMU_601: case POWERPC_MMU_601:
@ -1961,16 +1981,20 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
case POWERPC_MMU_SOFT_4xx_Z: case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
break; break;
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_REAL:
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
break; break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE MMU model is not implemented\n");
break; break;
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n"); cpu_abort(env, "BookE FSL MMU model is not implemented\n");
break; break;
case POWERPC_MMU_32B: case POWERPC_MMU_32B:
case POWERPC_MMU_601: case POWERPC_MMU_601:
@ -2613,6 +2637,10 @@ static always_inline void powerpc_excp (CPUState *env,
cpu_abort(env, "Floating point assist exception " cpu_abort(env, "Floating point assist exception "
"is not implemented yet !\n"); "is not implemented yet !\n");
goto store_next; goto store_next;
case POWERPC_EXCP_DABR: /* Data address breakpoint */
/* XXX: TODO */
cpu_abort(env, "DABR exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
/* XXX: TODO */ /* XXX: TODO */
cpu_abort(env, "IABR exception is not implemented yet !\n"); cpu_abort(env, "IABR exception is not implemented yet !\n");
@ -2648,6 +2676,16 @@ static always_inline void powerpc_excp (CPUState *env,
cpu_abort(env, cpu_abort(env,
"970 maintenance exception is not implemented yet !\n"); "970 maintenance exception is not implemented yet !\n");
goto store_next; goto store_next;
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
/* XXX: TODO */
cpu_abort(env, "Maskable external exception "
"is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
/* XXX: TODO */
cpu_abort(env, "Non maskable external exception "
"is not implemented yet !\n");
goto store_next;
default: default:
excp_invalid: excp_invalid:
cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
@ -2899,7 +2937,7 @@ void cpu_ppc_reset (void *opaque)
msr |= (target_ulong)1 << MSR_PR; msr |= (target_ulong)1 << MSR_PR;
#else #else
env->nip = env->hreset_vector | env->excp_prefix; env->nip = env->hreset_vector | env->excp_prefix;
if (env->mmu_model != POWERPC_MMU_REAL_4xx) if (env->mmu_model != POWERPC_MMU_REAL)
ppc_tlb_invalidate_all(env); ppc_tlb_invalidate_all(env);
#endif #endif
env->msr = msr; env->msr = msr;

17
target-ppc/translate_init.c
View File

@ -2656,7 +2656,7 @@ static int check_pow_hid0 (CPUPPCState *env)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
#define POWERPC_MSRM_401 (0x00000000000FD201ULL) #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx) #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x) #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401) #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_401 (bfd_mach_ppc_403) #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
@ -2775,7 +2775,7 @@ static void init_proc_IOP480 (CPUPPCState *env)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
#define POWERPC_MSRM_403 (0x000000000007D00DULL) #define POWERPC_MSRM_403 (0x000000000007D00DULL)
#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx) #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x) #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401) #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_403 (bfd_mach_ppc_403) #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
@ -6639,8 +6639,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
mmu_model = "PowerPC 4xx with software driven TLBs " mmu_model = "PowerPC 4xx with software driven TLBs "
"and zones protections"; "and zones protections";
break; break;
case POWERPC_MMU_REAL_4xx: case POWERPC_MMU_REAL:
mmu_model = "PowerPC 4xx real mode only"; mmu_model = "PowerPC real mode only";
break;
case POWERPC_MMU_MPC8xx:
mmu_model = "PowerPC MPC8xx";
break; break;
case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE:
mmu_model = "PowerPC BookE"; mmu_model = "PowerPC BookE";
@ -6648,6 +6651,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
case POWERPC_MMU_BOOKE_FSL: case POWERPC_MMU_BOOKE_FSL:
mmu_model = "PowerPC BookE FSL"; mmu_model = "PowerPC BookE FSL";
break; break;
case POWERPC_MMU_601:
mmu_model = "PowerPC 601";
break;
#if defined (TARGET_PPC64) #if defined (TARGET_PPC64)
case POWERPC_MMU_64B: case POWERPC_MMU_64B:
mmu_model = "PowerPC 64"; mmu_model = "PowerPC 64";
@ -6713,6 +6719,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
case PPC_FLAGS_INPUT_401: case PPC_FLAGS_INPUT_401:
bus_model = "PowerPC 401/403"; bus_model = "PowerPC 401/403";
break; break;
case PPC_FLAGS_INPUT_RCPU:
bus_model = "RCPU / MPC8xx";
break;
#if defined (TARGET_PPC64) #if defined (TARGET_PPC64)
case PPC_FLAGS_INPUT_970: case PPC_FLAGS_INPUT_970:
bus_model = "PowerPC 970"; bus_model = "PowerPC 970";