mirror of https://github.com/xemu-project/xemu.git
target/ppc: implement xscvqp[su]qz
Implement the following PowerISA v3.1 instructions: xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-9-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -2925,6 +2925,27 @@ VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
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VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
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VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
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VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
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VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
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#define VSX_CVT_FP_TO_INT128(op, tp, rnan) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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{ \
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ppc_vsr_t t; \
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int flags; \
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\
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helper_reset_fpstatus(env); \
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t.s128 = float128_to_##tp##_round_to_zero(xb->f128, &env->fp_status); \
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flags = get_float_exception_flags(&env->fp_status); \
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if (unlikely(flags & float_flag_invalid)) { \
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t.VsrD(0) = float_invalid_cvt(env, flags, t.VsrD(0), rnan, 0, GETPC());\
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t.VsrD(1) = -(t.VsrD(0) & 1); \
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} \
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\
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*xt = t; \
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do_float_check_status(env, GETPC()); \
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}
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VSX_CVT_FP_TO_INT128(XSCVQPUQZ, uint128, 0)
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VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
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/*
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/*
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* Likewise, except that the result is duplicated into both subwords.
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* Likewise, except that the result is duplicated into both subwords.
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* Power ISA v3.1 has Programming Notes for these insns:
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* Power ISA v3.1 has Programming Notes for these insns:
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@ -388,6 +388,8 @@ DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
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DEF_HELPER_3(XSCVQPUQZ, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVQPSQZ, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
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DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
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DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
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@ -695,6 +695,8 @@ XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
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## VSX Binary Floating-Point Convert Instructions
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## VSX Binary Floating-Point Convert Instructions
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XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
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XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
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XSCVQPUQZ 111111 ..... 00000 ..... 1101000100 - @X_tb
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XSCVQPSQZ 111111 ..... 01000 ..... 1101000100 - @X_tb
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XSCVUQQP 111111 ..... 00011 ..... 1101000100 - @X_tb
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XSCVUQQP 111111 ..... 00011 ..... 1101000100 - @X_tb
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XSCVSQQP 111111 ..... 01011 ..... 1101000100 - @X_tb
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XSCVSQQP 111111 ..... 01011 ..... 1101000100 - @X_tb
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XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
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XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
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@ -857,6 +857,8 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb *a,
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TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
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TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
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TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
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TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
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TRANS(XSCVQPUQZ, do_helper_env_X_tb, gen_helper_XSCVQPUQZ)
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TRANS(XSCVQPSQZ, do_helper_env_X_tb, gen_helper_XSCVQPSQZ)
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#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
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#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
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static void gen_##name(DisasContext *ctx) \
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static void gen_##name(DisasContext *ctx) \
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