mirror of https://github.com/xemu-project/xemu.git
hw/cxl: Line length reductions
Michael Tsirkin observed that there were some unnecessarily long lines in the CXL code in a recent review. This patch is intended to rectify that where it does not hurt readability. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Fan Ni <fan.ni@samsung.com> Message-Id: <20231023140210.3089-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
b34ae3c906
commit
b342489ae7
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@ -60,7 +60,8 @@ static void ct3_build_cdat(CDATObject *cdat, Error **errp)
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return;
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return;
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}
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}
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cdat->built_buf_len = cdat->build_cdat_table(&cdat->built_buf, cdat->private);
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cdat->built_buf_len = cdat->build_cdat_table(&cdat->built_buf,
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cdat->private);
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if (!cdat->built_buf_len) {
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if (!cdat->built_buf_len) {
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/* Build later as not all data available yet */
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/* Build later as not all data available yet */
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@ -241,7 +241,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
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POISON_ON_ERR_CAP, 0);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
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HDM_DECODER_ENABLE, 0);
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HDM_DECODER_ENABLE, 0);
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write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
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write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
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@ -264,15 +265,16 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
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}
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}
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}
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}
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void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk,
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void cxl_component_register_init_common(uint32_t *reg_state,
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uint32_t *write_msk,
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enum reg_type type)
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enum reg_type type)
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{
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{
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int caps = 0;
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int caps = 0;
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/*
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/*
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* In CXL 2.0 the capabilities required for each CXL component are such that,
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* In CXL 2.0 the capabilities required for each CXL component are such
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* with the ordering chosen here, a single number can be used to define
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* that, with the ordering chosen here, a single number can be used to
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* which capabilities should be provided.
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* define which capabilities should be provided.
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*/
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*/
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switch (type) {
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switch (type) {
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case CXL2_DOWNSTREAM_PORT:
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case CXL2_DOWNSTREAM_PORT:
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@ -449,7 +451,7 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
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default: /* Registers are RO for other component types */
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default: /* Registers are RO for other component types */
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break;
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break;
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}
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}
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/* There are rw1cs bits in the status register but never set currently */
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/* There are rw1cs bits in the status register but never set */
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break;
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break;
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}
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}
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@ -170,8 +170,10 @@ CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl,
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if (log->overflow_err_count) {
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if (log->overflow_err_count) {
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pl->flags |= CXL_GET_EVENT_FLAG_OVERFLOW;
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pl->flags |= CXL_GET_EVENT_FLAG_OVERFLOW;
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pl->overflow_err_count = cpu_to_le16(log->overflow_err_count);
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pl->overflow_err_count = cpu_to_le16(log->overflow_err_count);
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pl->first_overflow_timestamp = cpu_to_le64(log->first_overflow_timestamp);
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pl->first_overflow_timestamp =
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pl->last_overflow_timestamp = cpu_to_le64(log->last_overflow_timestamp);
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cpu_to_le64(log->first_overflow_timestamp);
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pl->last_overflow_timestamp =
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cpu_to_le64(log->last_overflow_timestamp);
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}
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}
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pl->record_count = cpu_to_le16(nr);
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pl->record_count = cpu_to_le16(nr);
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@ -180,7 +182,8 @@ CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl,
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return CXL_MBOX_SUCCESS;
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return CXL_MBOX_SUCCESS;
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}
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}
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CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds, CXLClearEventPayload *pl)
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CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds,
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CXLClearEventPayload *pl)
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{
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{
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CXLEventLog *log;
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CXLEventLog *log;
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uint8_t log_type;
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uint8_t log_type;
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@ -366,9 +366,12 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd,
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snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
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snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
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stq_le_p(&id->total_capacity, cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&id->total_capacity,
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stq_le_p(&id->persistent_capacity, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
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cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&id->volatile_capacity, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&id->persistent_capacity,
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cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&id->volatile_capacity,
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cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER);
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stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d));
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stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d));
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/* 256 poison records */
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/* 256 poison records */
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st24_le_p(id->poison_list_max_mer, 256);
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st24_le_p(id->poison_list_max_mer, 256);
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@ -396,13 +399,15 @@ static CXLRetCode cmd_ccls_get_partition_info(struct cxl_cmd *cmd,
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return CXL_MBOX_INTERNAL_ERROR;
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return CXL_MBOX_INTERNAL_ERROR;
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}
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}
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stq_le_p(&part_info->active_vmem, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&part_info->active_vmem,
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cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER);
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/*
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/*
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* When both next_vmem and next_pmem are 0, there is no pending change to
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* When both next_vmem and next_pmem are 0, there is no pending change to
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* partitioning.
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* partitioning.
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*/
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*/
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stq_le_p(&part_info->next_vmem, 0);
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stq_le_p(&part_info->next_vmem, 0);
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stq_le_p(&part_info->active_pmem, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&part_info->active_pmem,
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cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&part_info->next_pmem, 0);
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stq_le_p(&part_info->next_pmem, 0);
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*len = sizeof(*part_info);
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*len = sizeof(*part_info);
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@ -681,8 +686,10 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
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[FIRMWARE_UPDATE][GET_INFO] = { "FIRMWARE_UPDATE_GET_INFO",
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[FIRMWARE_UPDATE][GET_INFO] = { "FIRMWARE_UPDATE_GET_INFO",
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cmd_firmware_update_get_info, 0, 0 },
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cmd_firmware_update_get_info, 0, 0 },
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[TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
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[TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
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[TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE },
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[TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set,
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[LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0, 0 },
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8, IMMEDIATE_POLICY_CHANGE },
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[LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported,
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0, 0 },
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[LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
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[LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
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[IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
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[IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
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cmd_identify_memory_device, 0, 0 },
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cmd_identify_memory_device, 0, 0 },
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@ -208,10 +208,9 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
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}
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}
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if (nonvolatile_mr) {
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if (nonvolatile_mr) {
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uint64_t base = volatile_mr ? memory_region_size(volatile_mr) : 0;
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rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++,
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rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++,
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nonvolatile_mr, true,
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nonvolatile_mr, true, base);
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(volatile_mr ?
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memory_region_size(volatile_mr) : 0));
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if (rc < 0) {
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if (rc < 0) {
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goto error_cleanup;
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goto error_cleanup;
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}
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}
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@ -514,7 +513,8 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
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case A_CXL_RAS_UNC_ERR_STATUS:
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case A_CXL_RAS_UNC_ERR_STATUS:
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{
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{
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uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL);
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uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL);
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uint32_t fe = FIELD_EX32(capctrl, CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER);
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uint32_t fe = FIELD_EX32(capctrl, CXL_RAS_ERR_CAP_CTRL,
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FIRST_ERROR_POINTER);
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CXLError *cxl_err;
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CXLError *cxl_err;
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uint32_t unc_err;
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uint32_t unc_err;
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@ -533,7 +533,8 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
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* closest to behavior of hardware not capable of multiple
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* closest to behavior of hardware not capable of multiple
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* header recording.
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* header recording.
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*/
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*/
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QTAILQ_FOREACH_SAFE(cxl_err, &ct3d->error_list, node, cxl_next) {
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QTAILQ_FOREACH_SAFE(cxl_err, &ct3d->error_list, node,
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cxl_next) {
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if ((1 << cxl_err->type) & value) {
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if ((1 << cxl_err->type) & value) {
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QTAILQ_REMOVE(&ct3d->error_list, cxl_err, node);
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QTAILQ_REMOVE(&ct3d->error_list, cxl_err, node);
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g_free(cxl_err);
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g_free(cxl_err);
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@ -1072,7 +1073,8 @@ void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
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if (((start >= p->start) && (start < p->start + p->length)) ||
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if (((start >= p->start) && (start < p->start + p->length)) ||
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((start + length > p->start) &&
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((start + length > p->start) &&
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(start + length <= p->start + p->length))) {
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(start + length <= p->start + p->length))) {
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error_setg(errp, "Overlap with existing poisoned region not supported");
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error_setg(errp,
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"Overlap with existing poisoned region not supported");
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return;
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return;
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}
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}
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}
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}
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@ -1085,7 +1087,8 @@ void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
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p = g_new0(CXLPoison, 1);
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p = g_new0(CXLPoison, 1);
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p->length = length;
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p->length = length;
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p->start = start;
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p->start = start;
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p->type = CXL_POISON_TYPE_INTERNAL; /* Different from injected via the mbox */
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/* Different from injected via the mbox */
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p->type = CXL_POISON_TYPE_INTERNAL;
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QLIST_INSERT_HEAD(&ct3d->poison_list, p, node);
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QLIST_INSERT_HEAD(&ct3d->poison_list, p, node);
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ct3d->poison_list_cnt++;
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ct3d->poison_list_cnt++;
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@ -1222,7 +1225,8 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
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return;
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return;
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}
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}
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/* If the error is masked, nothting to do here */
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/* If the error is masked, nothting to do here */
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if (!((1 << cxl_err_type) & ~ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK))) {
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if (!((1 << cxl_err_type) &
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~ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK))) {
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return;
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return;
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}
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}
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@ -1372,7 +1376,8 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
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bool has_bank, uint8_t bank,
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bool has_bank, uint8_t bank,
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bool has_row, uint32_t row,
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bool has_row, uint32_t row,
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bool has_column, uint16_t column,
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bool has_column, uint16_t column,
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bool has_correction_mask, uint64List *correction_mask,
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bool has_correction_mask,
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uint64List *correction_mask,
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Error **errp)
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Error **errp)
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{
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{
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Object *obj = object_resolve_path(path, NULL);
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Object *obj = object_resolve_path(path, NULL);
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@ -1473,7 +1478,7 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
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int16_t temperature,
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int16_t temperature,
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uint32_t dirty_shutdown_count,
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uint32_t dirty_shutdown_count,
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uint32_t corrected_volatile_error_count,
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uint32_t corrected_volatile_error_count,
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uint32_t corrected_persistent_error_count,
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uint32_t corrected_persist_error_count,
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Error **errp)
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Error **errp)
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{
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{
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Object *obj = object_resolve_path(path, NULL);
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Object *obj = object_resolve_path(path, NULL);
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@ -1513,8 +1518,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
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module.life_used = life_used;
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module.life_used = life_used;
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stw_le_p(&module.temperature, temperature);
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stw_le_p(&module.temperature, temperature);
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stl_le_p(&module.dirty_shutdown_count, dirty_shutdown_count);
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stl_le_p(&module.dirty_shutdown_count, dirty_shutdown_count);
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stl_le_p(&module.corrected_volatile_error_count, corrected_volatile_error_count);
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stl_le_p(&module.corrected_volatile_error_count,
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stl_le_p(&module.corrected_persistent_error_count, corrected_persistent_error_count);
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corrected_volatile_error_count);
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stl_le_p(&module.corrected_persistent_error_count,
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corrected_persist_error_count);
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if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&module)) {
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if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&module)) {
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cxl_event_irq_assert(ct3d);
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cxl_event_irq_assert(ct3d);
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@ -33,7 +33,8 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
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bool has_bank, uint8_t bank,
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bool has_bank, uint8_t bank,
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bool has_row, uint32_t row,
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bool has_row, uint32_t row,
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bool has_column, uint16_t column,
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bool has_column, uint16_t column,
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bool has_correction_mask, uint64List *correction_mask,
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bool has_correction_mask,
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uint64List *correction_mask,
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Error **errp) {}
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Error **errp) {}
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void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
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void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
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@ -45,7 +46,7 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
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int16_t temperature,
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int16_t temperature,
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uint32_t dirty_shutdown_count,
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uint32_t dirty_shutdown_count,
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uint32_t corrected_volatile_error_count,
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uint32_t corrected_volatile_error_count,
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uint32_t corrected_persistent_error_count,
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uint32_t corrected_persist_error_count,
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Error **errp) {}
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Error **errp) {}
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void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
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void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
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@ -175,7 +175,8 @@ HDM_DECODER_INIT(3);
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(CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE)
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(CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE)
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#define CXL_SNOOP_REGISTERS_SIZE 0x8
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#define CXL_SNOOP_REGISTERS_SIZE 0x8
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QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) >= 0x1000,
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QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET +
|
||||||
|
CXL_SNOOP_REGISTERS_SIZE) >= 0x1000,
|
||||||
"No space for registers");
|
"No space for registers");
|
||||||
|
|
||||||
typedef struct component_registers {
|
typedef struct component_registers {
|
||||||
|
|
|
@ -192,7 +192,7 @@ void cxl_device_register_init_common(CXLDeviceState *dev);
|
||||||
* Documented as a 128 bit register, but 64 bit accesses and the second
|
* Documented as a 128 bit register, but 64 bit accesses and the second
|
||||||
* 64 bits are currently reserved.
|
* 64 bits are currently reserved.
|
||||||
*/
|
*/
|
||||||
REG64(CXL_DEV_CAP_ARRAY, 0) /* Documented as 128 bit register but 64 byte accesses */
|
REG64(CXL_DEV_CAP_ARRAY, 0)
|
||||||
FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
|
FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
|
||||||
FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
|
FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
|
||||||
FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
|
FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
|
||||||
|
@ -361,7 +361,8 @@ struct CXLType3Class {
|
||||||
uint64_t offset);
|
uint64_t offset);
|
||||||
void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
|
void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
|
||||||
uint64_t offset);
|
uint64_t offset);
|
||||||
bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t *data);
|
bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset,
|
||||||
|
uint8_t *data);
|
||||||
};
|
};
|
||||||
|
|
||||||
MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
|
MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
|
||||||
|
|
|
@ -92,7 +92,8 @@ typedef enum CXLEventIntMode {
|
||||||
CXL_INT_RES = 0x03,
|
CXL_INT_RES = 0x03,
|
||||||
} CXLEventIntMode;
|
} CXLEventIntMode;
|
||||||
#define CXL_EVENT_INT_MODE_MASK 0x3
|
#define CXL_EVENT_INT_MODE_MASK 0x3
|
||||||
#define CXL_EVENT_INT_SETTING(vector) ((((uint8_t)vector & 0xf) << 4) | CXL_INT_MSI_MSIX)
|
#define CXL_EVENT_INT_SETTING(vector) \
|
||||||
|
((((uint8_t)vector & 0xf) << 4) | CXL_INT_MSI_MSIX)
|
||||||
typedef struct CXLEventInterruptPolicy {
|
typedef struct CXLEventInterruptPolicy {
|
||||||
uint8_t info_settings;
|
uint8_t info_settings;
|
||||||
uint8_t warn_settings;
|
uint8_t warn_settings;
|
||||||
|
|
Loading…
Reference in New Issue