From b29a0341d7ed7e7df4bf77a41db8e614f1ddb645 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 24 Jan 2007 18:01:23 +0000
Subject: [PATCH] EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
---
target-mips/cpu.h | 2 +-
target-mips/op.c | 19 ++-----------------
target-mips/translate.c | 6 +++---
3 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3c99054d6d..fb5a3fef3d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -162,7 +162,7 @@ struct CPUMIPSState {
#define CP0Ca_EC 2
target_ulong CP0_EPC;
int32_t CP0_PRid;
- target_ulong CP0_EBase;
+ int32_t CP0_EBase;
int32_t CP0_Config0;
#define CP0C0_M 31
#define CP0C0_K23 28
diff --git a/target-mips/op.c b/target-mips/op.c
index 9d30d03cd3..cd5c69ca46 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1158,7 +1158,7 @@ void op_mfc0_prid (void)
void op_mfc0_ebase (void)
{
- T0 = (int32_t)env->CP0_EBase;
+ T0 = env->CP0_EBase;
RETURN();
}
@@ -1423,7 +1423,7 @@ void op_mtc0_ebase (void)
{
/* vectored interrupts not implemented */
/* Multi-CPU not implemented */
- env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
+ env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
RETURN();
}
@@ -1563,12 +1563,6 @@ void op_dmfc0_epc (void)
RETURN();
}
-void op_dmfc0_ebase (void)
-{
- T0 = env->CP0_EBase;
- RETURN();
-}
-
void op_dmfc0_lladdr (void)
{
T0 = env->CP0_LLAddr >> 4;
@@ -1627,15 +1621,6 @@ void op_dmtc0_epc (void)
RETURN();
}
-void op_dmtc0_ebase (void)
-{
- /* vectored interrupts not implemented */
- /* Multi-CPU not implemented */
- /* XXX: 64bit addressing broken */
- env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
- RETURN();
-}
-
void op_dmtc0_watchlo0 (void)
{
env->CP0_WatchLo = T0;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 3cc8a55d4e..ce56bb0834 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -3099,7 +3099,7 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
rn = "PRid";
break;
case 1:
- gen_op_dmfc0_ebase();
+ gen_op_mfc0_ebase();
rn = "EBase";
break;
default:
@@ -3683,7 +3683,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
rn = "PRid";
break;
case 1:
- gen_op_dmtc0_ebase();
+ gen_op_mtc0_ebase();
rn = "EBase";
break;
default:
@@ -5305,7 +5305,7 @@ void cpu_reset (CPUMIPSState *env)
#endif
env->CP0_Wired = 0;
/* SMP not implemented */
- env->CP0_EBase = (int32_t)0x80000000;
+ env->CP0_EBase = 0x80000000;
env->CP0_Config0 = MIPS_CONFIG0;
env->CP0_Config1 = MIPS_CONFIG1;
env->CP0_Config2 = MIPS_CONFIG2;