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target-mips: add MSA exceptions 

add MSA exceptions

Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Yongbok Kim 2014-11-01 05:28:36 +00:00 committed by Leon Alrae
parent e97a391d20
commit b10ac20446
1 changed files with 10 additions and 0 deletions
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10
target-mips/helper.c
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@ -426,6 +426,8 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_CACHE] = "cache error", [EXCP_CACHE] = "cache error",
[EXCP_TLBXI] = "TLB execute-inhibit", [EXCP_TLBXI] = "TLB execute-inhibit",
[EXCP_TLBRI] = "TLB read-inhibit", [EXCP_TLBRI] = "TLB read-inhibit",
[EXCP_MSADIS] = "MSA disabled",
[EXCP_MSAFPE] = "MSA floating point",
}; };
target_ulong exception_resume_pc (CPUMIPSState *env) target_ulong exception_resume_pc (CPUMIPSState *env)
@ -667,6 +669,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
cause = 13; cause = 13;
update_badinstr = 1; update_badinstr = 1;
goto set_EPC; goto set_EPC;
case EXCP_MSAFPE:
cause = 14;
update_badinstr = 1;
goto set_EPC;
case EXCP_FPE: case EXCP_FPE:
cause = 15; cause = 15;
update_badinstr = 1; update_badinstr = 1;
@ -681,6 +687,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_TLBXI: case EXCP_TLBXI:
cause = 20; cause = 20;
goto set_EPC; goto set_EPC;
case EXCP_MSADIS:
cause = 21;
update_badinstr = 1;
goto set_EPC;
case EXCP_MDMX: case EXCP_MDMX:
cause = 22; cause = 22;
goto set_EPC; goto set_EPC;