mirror of https://github.com/xemu-project/xemu.git
tcg/s390: Implement field extraction opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -78,7 +78,7 @@ extern uint64_t s390_facilities;
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
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#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
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#define TCG_TARGET_HAS_extract_i32 0
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#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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@ -109,7 +109,7 @@ extern uint64_t s390_facilities;
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
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#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
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#define TCG_TARGET_HAS_extract_i64 0
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#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -1252,6 +1252,12 @@ static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
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tcg_out_risbg(s, dest, src, msb, lsb, ofs, 0);
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tcg_out_risbg(s, dest, src, msb, lsb, ofs, 0);
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}
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}
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static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
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int ofs, int len)
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{
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tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
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}
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static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
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static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
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{
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{
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ptrdiff_t off = dest - s->code_ptr;
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ptrdiff_t off = dest - s->code_ptr;
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@ -2158,6 +2164,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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OP_32_64(deposit):
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OP_32_64(deposit):
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tgen_deposit(s, args[0], args[2], args[3], args[4]);
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tgen_deposit(s, args[0], args[2], args[3], args[4]);
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break;
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break;
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OP_32_64(extract):
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tgen_extract(s, args[0], args[1], args[2], args[3]);
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break;
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case INDEX_op_mb:
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case INDEX_op_mb:
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/* The host memory model is quite strong, we simply need to
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/* The host memory model is quite strong, we simply need to
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@ -2227,6 +2236,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
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{ INDEX_op_setcond_i32, { "r", "r", "rC" } },
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{ INDEX_op_setcond_i32, { "r", "r", "rC" } },
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{ INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } },
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{ INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } },
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{ INDEX_op_deposit_i32, { "r", "0", "r" } },
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{ INDEX_op_deposit_i32, { "r", "0", "r" } },
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{ INDEX_op_extract_i32, { "r", "r" } },
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_ld_i64, { "r", "L" } },
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{ INDEX_op_qemu_ld_i64, { "r", "L" } },
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@ -2288,6 +2298,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
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{ INDEX_op_setcond_i64, { "r", "r", "rC" } },
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{ INDEX_op_setcond_i64, { "r", "r", "rC" } },
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{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
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{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
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{ INDEX_op_deposit_i64, { "r", "0", "r" } },
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{ INDEX_op_deposit_i64, { "r", "0", "r" } },
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{ INDEX_op_extract_i64, { "r", "r" } },
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{ INDEX_op_mb, { } },
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{ INDEX_op_mb, { } },
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{ -1 },
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{ -1 },
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