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target/riscv: Remove gen_arith_div* 

Use ctx->w and the enhanced gen_arith function.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-8-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:12 -07:00 committed by Alistair Francis
parent 191d1dafae
commit afbbec8201
2 changed files with 8 additions and 50 deletions
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16
target/riscv/insn_trans/trans_rvm.c.inc
View File

@ -99,30 +99,30 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
{ {
REQUIRE_64BIT(ctx); REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM); REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith_div_w(ctx, a, &gen_div); return gen_arith(ctx, a, EXT_SIGN, gen_div);
} }
static bool trans_divuw(DisasContext *ctx, arg_divuw *a) static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{ {
REQUIRE_64BIT(ctx); REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM); REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith_div_uw(ctx, a, &gen_divu); return gen_arith(ctx, a, EXT_ZERO, gen_divu);
} }
static bool trans_remw(DisasContext *ctx, arg_remw *a) static bool trans_remw(DisasContext *ctx, arg_remw *a)
{ {
REQUIRE_64BIT(ctx); REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM); REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith_div_w(ctx, a, &gen_rem); return gen_arith(ctx, a, EXT_SIGN, gen_rem);
} }
static bool trans_remuw(DisasContext *ctx, arg_remuw *a) static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{ {
REQUIRE_64BIT(ctx); REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM); REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith_div_uw(ctx, a, &gen_remu); return gen_arith(ctx, a, EXT_ZERO, gen_remu);
} }

42
target/riscv/translate.c
View File

@ -507,48 +507,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
return true; return true;
} }
static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(ctx, source1, a->rs1);
gen_get_gpr(ctx, source2, a->rs2);
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
(*func)(source1, source1, source2);
tcg_gen_ext32s_tl(source1, source1);
gen_set_gpr(ctx, a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(ctx, source1, a->rs1);
gen_get_gpr(ctx, source2, a->rs2);
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
(*func)(source1, source1, source2);
tcg_gen_ext32s_tl(source1, source1);
gen_set_gpr(ctx, a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
{ {
tcg_gen_deposit_tl(ret, arg1, arg2, tcg_gen_deposit_tl(ret, arg1, arg2,