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target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
Rename the function to match gen_gvec_ool_arg_zpz, and move to be adjacent. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220527181907.189259-24-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -228,6 +228,11 @@ static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
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return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
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}
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static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
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arg_rpri_esz *a)
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{
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return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
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}
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/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
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static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
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@ -952,12 +957,6 @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
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return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
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}
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static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
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gen_helper_gvec_3 *fn)
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{
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return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
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}
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static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
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{
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static gen_helper_gvec_3 * const fns[4] = {
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@ -971,7 +970,7 @@ static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
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/* Shift by element size is architecturally valid. For
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arithmetic right-shift, it's the same as by one less. */
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a->imm = MIN(a->imm, (8 << a->esz) - 1);
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
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@ -988,7 +987,7 @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
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if (a->imm >= (8 << a->esz)) {
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return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
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} else {
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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}
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@ -1006,7 +1005,7 @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
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if (a->imm >= (8 << a->esz)) {
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return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
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} else {
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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}
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@ -1024,7 +1023,7 @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
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if (a->imm >= (8 << a->esz)) {
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return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
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} else {
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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}
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@ -1037,7 +1036,7 @@ static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
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if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
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@ -1049,7 +1048,7 @@ static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
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if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
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@ -1061,7 +1060,7 @@ static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
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if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
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@ -1073,7 +1072,7 @@ static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
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if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
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@ -1085,7 +1084,7 @@ static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
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if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_zpzi_ool(s, a, fns[a->esz]);
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return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
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}
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/*
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