mirror of https://github.com/xemu-project/xemu.git
openpic: fix coding style issues
This patch fixes the following coding style violations: - structs have to be typedef and be CamelCase - if()s are always surrounded by curly braces Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
d56af005dc
commit
af7e9e74c6
100
hw/openpic.c
100
hw/openpic.c
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@ -173,19 +173,19 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
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static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
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uint32_t val, int idx);
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typedef struct IRQ_queue_t {
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typedef struct IRQQueue {
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uint32_t queue[BF_WIDTH(MAX_IRQ)];
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int next;
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int priority;
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int pending; /* nr of pending bits in queue */
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} IRQ_queue_t;
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} IRQQueue;
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typedef struct IRQ_src_t {
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typedef struct IRQSource {
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uint32_t ipvp; /* IRQ vector/priority register */
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uint32_t ide; /* IRQ destination register */
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int last_cpu;
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int pending; /* TRUE if IRQ is pending */
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} IRQ_src_t;
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} IRQSource;
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#define IPVP_MASK_SHIFT 31
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#define IPVP_MASK_MASK (1 << IPVP_MASK_SHIFT)
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@ -206,12 +206,12 @@ typedef struct IRQ_src_t {
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#define IDE_EP 0x80000000 /* external pin */
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#define IDE_CI 0x40000000 /* critical interrupt */
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typedef struct IRQ_dst_t {
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typedef struct IRQDest {
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uint32_t pctp; /* CPU current task priority */
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IRQ_queue_t raised;
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IRQ_queue_t servicing;
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IRQQueue raised;
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IRQQueue servicing;
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qemu_irq *irqs;
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} IRQ_dst_t;
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} IRQDest;
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typedef struct OpenPICState {
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SysBusDevice busdev;
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@ -239,9 +239,9 @@ typedef struct OpenPICState {
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uint32_t spve; /* Spurious vector register */
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uint32_t tifr; /* Timer frequency reporting register */
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/* Source registers */
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IRQ_src_t src[MAX_IRQ];
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IRQSource src[MAX_IRQ];
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/* Local registers per output pin */
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IRQ_dst_t dst[MAX_CPU];
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IRQDest dst[MAX_CPU];
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uint32_t nb_cpus;
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/* Timer registers */
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struct {
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@ -258,26 +258,26 @@ typedef struct OpenPICState {
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uint32_t irq_msi;
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} OpenPICState;
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQSource *src);
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static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ)
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static inline void IRQ_setbit(IRQQueue *q, int n_IRQ)
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{
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q->pending++;
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set_bit(q->queue, n_IRQ);
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}
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static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ)
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static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ)
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{
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q->pending--;
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reset_bit(q->queue, n_IRQ);
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}
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static inline int IRQ_testbit(IRQ_queue_t *q, int n_IRQ)
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static inline int IRQ_testbit(IRQQueue *q, int n_IRQ)
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{
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return test_bit(q->queue, n_IRQ);
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}
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static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
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static void IRQ_check(OpenPICState *opp, IRQQueue *q)
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{
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int next, i;
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int priority;
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@ -306,7 +306,7 @@ out:
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q->priority = priority;
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}
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static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q)
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static int IRQ_get_next(OpenPICState *opp, IRQQueue *q)
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{
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if (q->next == -1) {
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/* XXX: optimize */
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@ -318,8 +318,8 @@ static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q)
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static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ)
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{
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IRQ_dst_t *dst;
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IRQ_src_t *src;
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IRQDest *dst;
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IRQSource *src;
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int priority;
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dst = &opp->dst[n_CPU];
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@ -360,7 +360,7 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ)
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/* update pic state because registers for n_IRQ have changed value */
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static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
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{
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IRQ_src_t *src;
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IRQSource *src;
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int i;
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src = &opp->src[n_IRQ];
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@ -404,8 +404,9 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
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} else {
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/* Distributed delivery mode */
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for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
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if (i == opp->nb_cpus)
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if (i == opp->nb_cpus) {
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i = 0;
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}
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if (src->ide & (1 << i)) {
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IRQ_local_pipe(opp, i, n_IRQ);
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src->last_cpu = i;
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@ -418,7 +419,7 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
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static void openpic_set_irq(void *opaque, int n_IRQ, int level)
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{
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OpenPICState *opp = opaque;
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IRQ_src_t *src;
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IRQSource *src;
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src = &opp->src[n_IRQ];
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DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
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@ -431,8 +432,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
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}
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} else {
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/* edge-sensitive irq */
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if (level)
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if (level) {
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src->pending = 1;
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}
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}
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openpic_update_irq(opp, n_IRQ);
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}
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@ -459,9 +461,9 @@ static void openpic_reset(DeviceState *d)
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/* Initialise IRQ destinations */
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for (i = 0; i < MAX_CPU; i++) {
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opp->dst[i].pctp = 15;
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memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
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memset(&opp->dst[i].raised, 0, sizeof(IRQQueue));
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opp->dst[i].raised.next = -1;
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memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
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memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue));
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opp->dst[i].servicing.next = -1;
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}
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/* Initialise timers */
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@ -508,12 +510,13 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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OpenPICState *opp = opaque;
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IRQ_dst_t *dst;
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IRQDest *dst;
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int idx;
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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if (addr & 0xF) {
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return;
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}
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switch (addr) {
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case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
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break;
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@ -575,8 +578,9 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
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DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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if (addr & 0xF) {
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return retval;
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}
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switch (addr) {
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case 0x1000: /* FREP */
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retval = opp->frep;
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@ -631,8 +635,9 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
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int idx;
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DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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if (addr & 0xF) {
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return;
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}
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idx = (addr >> 6) & 0x3;
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addr = addr & 0x30;
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@ -705,8 +710,9 @@ static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
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int idx;
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DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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if (addr & 0xF) {
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return;
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}
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addr = addr & 0xFFF0;
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idx = addr >> 5;
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if (addr & 0x10) {
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@ -726,8 +732,9 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
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DPRINTF("%s: addr %08x\n", __func__, addr);
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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if (addr & 0xF) {
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return retval;
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}
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addr = addr & 0xFFF0;
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idx = addr >> 5;
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if (addr & 0x10) {
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@ -808,8 +815,8 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
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uint32_t val, int idx)
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{
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OpenPICState *opp = opaque;
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IRQ_src_t *src;
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IRQ_dst_t *dst;
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IRQSource *src;
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IRQDest *dst;
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int s_IRQ, n_IRQ;
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DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
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@ -819,8 +826,9 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
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return;
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}
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if (addr & 0xF)
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if (addr & 0xF) {
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return;
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}
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dst = &opp->dst[idx];
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addr &= 0xFF0;
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switch (addr) {
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@ -877,8 +885,8 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
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int idx)
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{
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OpenPICState *opp = opaque;
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IRQ_src_t *src;
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IRQ_dst_t *dst;
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IRQSource *src;
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IRQDest *dst;
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uint32_t retval;
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int n_IRQ;
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@ -889,8 +897,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
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return retval;
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}
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if (addr & 0xF)
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if (addr & 0xF) {
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return retval;
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}
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dst = &opp->dst[idx];
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addr &= 0xFF0;
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switch (addr) {
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@ -1059,7 +1068,7 @@ static const MemoryRegionOps openpic_msi_ops_be = {
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},
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};
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static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
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static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q)
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{
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unsigned int i;
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@ -1102,7 +1111,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
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}
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}
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static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
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static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
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{
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unsigned int i;
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@ -1118,8 +1127,9 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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OpenPICState *opp = (OpenPICState *)opaque;
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unsigned int i;
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if (version_id != 1)
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if (version_id != 1) {
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return -EINVAL;
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}
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qemu_get_be32s(f, &opp->glbc);
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qemu_get_be32s(f, &opp->veni);
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@ -1150,7 +1160,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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return 0;
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}
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQSource *src)
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{
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int n_ci = IDR_CI0_SHIFT - n_CPU;
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@ -1161,19 +1171,19 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
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}
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}
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struct memreg {
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typedef struct MemReg {
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const char *name;
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MemoryRegionOps const *ops;
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bool map;
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hwaddr start_addr;
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ram_addr_t size;
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};
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} MemReg;
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static int openpic_init(SysBusDevice *dev)
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{
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OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
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int i, j;
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struct memreg list_le[] = {
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MemReg list_le[] = {
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{"glb", &openpic_glb_ops_le, true,
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OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops_le, true,
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@ -1185,7 +1195,7 @@ static int openpic_init(SysBusDevice *dev)
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{"cpu", &openpic_cpu_ops_le, true,
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OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
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};
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struct memreg list_be[] = {
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MemReg list_be[] = {
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{"glb", &openpic_glb_ops_be, true,
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OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops_be, true,
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@ -1197,7 +1207,7 @@ static int openpic_init(SysBusDevice *dev)
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{"cpu", &openpic_cpu_ops_be, true,
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OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
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};
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struct memreg *list;
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MemReg *list;
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switch (opp->model) {
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case OPENPIC_MODEL_FSL_MPIC_20:
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