mirror of https://github.com/xemu-project/xemu.git
target/sparc: Move RDASR, STBAR, MEMBAR to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
3037663616
commit
af25071c1d
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@ -22,6 +22,28 @@ SETHI 00 rd:5 100 i:22
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CALL 01 i:s30
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{
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[
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STBAR 10 00000 101000 01111 0 0000000000000
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MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
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RDCCR 10 rd:5 101000 00010 0 0000000000000
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RDASI 10 rd:5 101000 00011 0 0000000000000
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RDTICK 10 rd:5 101000 00100 0 0000000000000
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RDPC 10 rd:5 101000 00101 0 0000000000000
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RDFPRS 10 rd:5 101000 00110 0 0000000000000
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RDASR17 10 rd:5 101000 10001 0 0000000000000
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RDGSR 10 rd:5 101000 10011 0 0000000000000
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RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
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RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
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RDSTICK 10 rd:5 101000 11000 0 0000000000000
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RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
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RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
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]
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# Before v8, all rs1 accepted; otherwise rs1==0.
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RDY 10 rd:5 101000 rs1:5 0 0000000000000
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}
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Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
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{
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# For v7, the entire simm13 field is present, but masked to 7 bits.
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@ -36,6 +36,11 @@
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#include "exec/helper-info.c.inc"
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#undef HELPER_H
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#ifndef TARGET_SPARC64
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# define gen_helper_rdccr(D, E) qemu_build_not_reached()
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# define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached()
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#endif
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/* Dynamic PC, must exit to main loop. */
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#define DYNAMIC_PC 1
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/* Dynamic PC, one of two values according to jump_pc[T2]. */
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@ -64,10 +69,21 @@ static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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#else
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static TCGv cpu_wim;
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# define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; })
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# define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; })
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# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
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# define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
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#endif
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/* Floating point registers */
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static TCGv_i64 cpu_fpr[TARGET_DPREGS];
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#define env_field_offsetof(X) offsetof(CPUSPARCState, X)
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#ifdef TARGET_SPARC64
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# define env64_field_offsetof(X) env_field_offsetof(X)
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#else
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# define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
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#endif
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typedef struct DisasDelayException {
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struct DisasDelayException *next;
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TCGLabel *lab;
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@ -2842,10 +2858,14 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
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#define avail_ALL(C) true
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#ifdef TARGET_SPARC64
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# define avail_32(C) false
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# define avail_ASR17(C) false
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# define avail_64(C) true
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# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
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#else
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# define avail_32(C) true
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# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
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# define avail_64(C) false
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# define avail_HYPV(C) false
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#endif
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/* Default case for non jump instructions. */
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@ -2947,6 +2967,12 @@ static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
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return true;
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}
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static bool raise_priv(DisasContext *dc)
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{
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gen_exception(dc, TT_PRIV_INSN);
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return true;
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}
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static bool do_bpcc(DisasContext *dc, arg_bcc *a)
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{
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target_long target = address_mask_i(dc, dc->pc + a->i * 4);
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@ -3117,6 +3143,183 @@ static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tcc_i_v9 *a)
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return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i);
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}
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static bool trans_STBAR(DisasContext *dc, arg_STBAR *a)
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{
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tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
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return advance_pc(dc);
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}
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static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a)
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{
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if (avail_32(dc)) {
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return false;
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}
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if (a->mmask) {
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/* Note TCG_MO_* was modeled on sparc64, so mmask matches. */
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tcg_gen_mb(a->mmask | TCG_BAR_SC);
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}
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if (a->cmask) {
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/* For #Sync, etc, end the TB to recognize interrupts. */
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dc->base.is_jmp = DISAS_EXIT;
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}
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return advance_pc(dc);
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}
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static bool do_rd_special(DisasContext *dc, bool priv, int rd,
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TCGv (*func)(DisasContext *, TCGv))
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{
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if (!priv) {
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return raise_priv(dc);
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}
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gen_store_gpr(dc, rd, func(dc, gen_dest_gpr(dc, rd)));
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return advance_pc(dc);
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}
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static TCGv do_rdy(DisasContext *dc, TCGv dst)
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{
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return cpu_y;
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}
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static bool trans_RDY(DisasContext *dc, arg_RDY *a)
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{
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/*
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* TODO: Need a feature bit for sparcv8. In the meantime, treat all
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* 32-bit cpus like sparcv7, which ignores the rs1 field.
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* This matches after all other ASR, so Leon3 Asr17 is handled first.
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*/
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if (avail_64(dc) && a->rs1 != 0) {
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return false;
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}
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return do_rd_special(dc, true, a->rd, do_rdy);
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}
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static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
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{
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uint32_t val;
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/*
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* TODO: There are many more fields to be filled,
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* some of which are writable.
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*/
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val = dc->def->nwindows - 1; /* [4:0] NWIN */
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val |= 1 << 8; /* [8] V8 */
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return tcg_constant_tl(val);
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}
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TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
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static TCGv do_rdccr(DisasContext *dc, TCGv dst)
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{
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update_psr(dc);
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gen_helper_rdccr(dst, tcg_env);
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return dst;
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}
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TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr)
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static TCGv do_rdasi(DisasContext *dc, TCGv dst)
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{
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#ifdef TARGET_SPARC64
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return tcg_constant_tl(dc->asi);
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#else
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qemu_build_not_reached();
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#endif
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}
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TRANS(RDASI, 64, do_rd_special, true, a->rd, do_rdasi)
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static TCGv do_rdtick(DisasContext *dc, TCGv dst)
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{
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TCGv_ptr r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
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if (translator_io_start(&dc->base)) {
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dc->base.is_jmp = DISAS_EXIT;
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}
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gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
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tcg_constant_i32(dc->mem_idx));
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return dst;
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}
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/* TODO: non-priv access only allowed when enabled. */
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TRANS(RDTICK, 64, do_rd_special, true, a->rd, do_rdtick)
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static TCGv do_rdpc(DisasContext *dc, TCGv dst)
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{
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return tcg_constant_tl(address_mask_i(dc, dc->pc));
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}
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TRANS(RDPC, 64, do_rd_special, true, a->rd, do_rdpc)
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static TCGv do_rdfprs(DisasContext *dc, TCGv dst)
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{
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tcg_gen_ext_i32_tl(dst, cpu_fprs);
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return dst;
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}
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TRANS(RDFPRS, 64, do_rd_special, true, a->rd, do_rdfprs)
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static TCGv do_rdgsr(DisasContext *dc, TCGv dst)
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{
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gen_trap_ifnofpu(dc);
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return cpu_gsr;
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}
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TRANS(RDGSR, 64, do_rd_special, true, a->rd, do_rdgsr)
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static TCGv do_rdsoftint(DisasContext *dc, TCGv dst)
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{
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tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(softint));
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return dst;
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}
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TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a->rd, do_rdsoftint)
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static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst)
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{
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return cpu_tick_cmpr;
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}
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/* TODO: non-priv access only allowed when enabled. */
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TRANS(RDTICK_CMPR, 64, do_rd_special, true, a->rd, do_rdtick_cmpr)
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static TCGv do_rdstick(DisasContext *dc, TCGv dst)
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{
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TCGv_ptr r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
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if (translator_io_start(&dc->base)) {
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dc->base.is_jmp = DISAS_EXIT;
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}
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gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
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tcg_constant_i32(dc->mem_idx));
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return dst;
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}
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/* TODO: non-priv access only allowed when enabled. */
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TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rdstick)
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static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst)
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{
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return cpu_stick_cmpr;
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}
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/* TODO: supervisor access only allowed when enabled by hypervisor. */
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TRANS(RDSTICK_CMPR, 64, do_rd_special, supervisor(dc), a->rd, do_rdstick_cmpr)
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/*
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* UltraSPARC-T1 Strand status.
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* HYPV check maybe not enough, UA2005 & UA2007 describe
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* this ASR as impl. dep
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*/
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static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst)
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{
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return tcg_constant_tl(1);
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}
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TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status)
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#define CHECK_IU_FEATURE(dc, FEATURE) \
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if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
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goto illegal_insn;
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@ -3143,134 +3346,12 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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g_assert_not_reached(); /* in decodetree */
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case 2: /* FPU & Logical Operations */
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{
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unsigned int xop = GET_FIELD(insn, 7, 12);
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TCGv cpu_dst = tcg_temp_new();
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TCGv cpu_tmp0;
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unsigned int xop __attribute__((unused)) = GET_FIELD(insn, 7, 12);
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TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
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TCGv cpu_tmp0 __attribute__((unused));
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if (xop == 0x28) {
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rs1 = GET_FIELD(insn, 13, 17);
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switch(rs1) {
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case 0: /* rdy */
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#ifndef TARGET_SPARC64
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case 0x01 ... 0x0e: /* undefined in the SPARCv8
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manual, rdy on the microSPARC
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II */
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case 0x0f: /* stbar in the SPARCv8 manual,
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rdy on the microSPARC II */
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case 0x10 ... 0x1f: /* implementation-dependent in the
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SPARCv8 manual, rdy on the
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microSPARC II */
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/* Read Asr17 */
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if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
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TCGv t = gen_dest_gpr(dc, rd);
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/* Read Asr17 for a Leon3 monoprocessor */
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tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
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gen_store_gpr(dc, rd, t);
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break;
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}
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#endif
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gen_store_gpr(dc, rd, cpu_y);
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break;
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#ifdef TARGET_SPARC64
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case 0x2: /* V9 rdccr */
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update_psr(dc);
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gen_helper_rdccr(cpu_dst, tcg_env);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x3: /* V9 rdasi */
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tcg_gen_movi_tl(cpu_dst, dc->asi);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x4: /* V9 rdtick */
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{
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TCGv_ptr r_tickptr;
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TCGv_i32 r_const;
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r_tickptr = tcg_temp_new_ptr();
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r_const = tcg_constant_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, tcg_env,
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offsetof(CPUSPARCState, tick));
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if (translator_io_start(&dc->base)) {
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dc->base.is_jmp = DISAS_EXIT;
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}
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gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr,
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r_const);
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gen_store_gpr(dc, rd, cpu_dst);
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}
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break;
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case 0x5: /* V9 rdpc */
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{
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TCGv t = gen_dest_gpr(dc, rd);
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if (unlikely(AM_CHECK(dc))) {
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tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
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} else {
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tcg_gen_movi_tl(t, dc->pc);
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}
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gen_store_gpr(dc, rd, t);
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}
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break;
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case 0x6: /* V9 rdfprs */
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tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0xf: /* V9 membar */
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break; /* no effect */
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case 0x13: /* Graphics Status */
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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gen_store_gpr(dc, rd, cpu_gsr);
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break;
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case 0x16: /* Softint */
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tcg_gen_ld32s_tl(cpu_dst, tcg_env,
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offsetof(CPUSPARCState, softint));
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x17: /* Tick compare */
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gen_store_gpr(dc, rd, cpu_tick_cmpr);
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break;
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case 0x18: /* System tick */
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{
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TCGv_ptr r_tickptr;
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TCGv_i32 r_const;
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r_tickptr = tcg_temp_new_ptr();
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r_const = tcg_constant_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, tcg_env,
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offsetof(CPUSPARCState, stick));
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if (translator_io_start(&dc->base)) {
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dc->base.is_jmp = DISAS_EXIT;
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}
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gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr,
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r_const);
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gen_store_gpr(dc, rd, cpu_dst);
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}
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break;
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case 0x19: /* System tick compare */
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gen_store_gpr(dc, rd, cpu_stick_cmpr);
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break;
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case 0x1a: /* UltraSPARC-T1 Strand status */
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/* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
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* this ASR as impl. dep
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*/
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CHECK_IU_FEATURE(dc, HYPV);
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{
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TCGv t = gen_dest_gpr(dc, rd);
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tcg_gen_movi_tl(t, 1UL);
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gen_store_gpr(dc, rd, t);
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}
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break;
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case 0x10: /* Performance Control */
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case 0x11: /* Performance Instrumentation Counter */
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case 0x12: /* Dispatch Control */
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case 0x14: /* Softint set, WO */
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case 0x15: /* Softint clear, WO */
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#endif
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default:
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goto illegal_insn;
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}
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#if !defined(CONFIG_USER_ONLY)
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} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
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if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
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#ifndef TARGET_SPARC64
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if (!supervisor(dc)) {
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goto priv_insn;
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@ -3308,7 +3389,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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#endif
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
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}
|
||||
if (xop == 0x2a) { /* rdwim / V9 rdpr */
|
||||
if (!supervisor(dc)) {
|
||||
goto priv_insn;
|
||||
}
|
||||
|
|
@ -3432,9 +3514,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
|
|||
#endif
|
||||
gen_store_gpr(dc, rd, cpu_tmp0);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
|
||||
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
|
||||
if (xop == 0x2b) { /* rdtbr / V9 flushw */
|
||||
#ifdef TARGET_SPARC64
|
||||
gen_helper_flushw(tcg_env);
|
||||
#else
|
||||
|
|
@ -3443,8 +3526,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
|
|||
gen_store_gpr(dc, rd, cpu_tbr);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
} else if (xop == 0x34) { /* FPU Operations */
|
||||
if (xop == 0x34) { /* FPU Operations */
|
||||
if (gen_trap_ifnofpu(dc)) {
|
||||
goto jmp_insn;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue