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omap_uart: convert to memory API 

Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-11-22 15:06:46 +02:00
parent f81138ce97
commit aee39503df
4 changed files with 34 additions and 26 deletions
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4
hw/nseries.c
View File

@ -33,6 +33,7 @@
#include "loader.h" #include "loader.h"
#include "blockdev.h" #include "blockdev.h"
#include "sysbus.h" #include "sysbus.h"
#include "exec-memory.h"
/* Nokia N8x0 support */ /* Nokia N8x0 support */
struct n800_s { struct n800_s {
@ -1275,11 +1276,12 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_cmdline, const char *initrd_filename, const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, struct arm_boot_info *binfo, int model) const char *cpu_model, struct arm_boot_info *binfo, int model)
{ {
MemoryRegion *sysmem = get_system_memory();
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
int sdram_size = binfo->ram_size; int sdram_size = binfo->ram_size;
DisplayState *ds; DisplayState *ds;
s->cpu = omap2420_mpu_init(sdram_size, cpu_model); s->cpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model);
/* Setup peripherals /* Setup peripherals
* *

6
hw/omap.h
View File

@ -658,7 +658,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
qemu_irq irq, omap_clk fclk, omap_clk iclk, qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr); const char *label, CharDriverState *chr);
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk, qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr); const char *label, CharDriverState *chr);
@ -952,7 +953,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
const char *core); const char *core);
/* omap2.c */ /* omap2.c */
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
const char *core); const char *core);
# if TARGET_PHYS_ADDR_BITS == 32 # if TARGET_PHYS_ADDR_BITS == 32

9
hw/omap2.c
View File

@ -2223,7 +2223,8 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
{ 0, OMAP_INT_24XX_SDMA_IRQ3 }, { 0, OMAP_INT_24XX_SDMA_IRQ3 },
}; };
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
const char *core) const char *core)
{ {
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
@ -2295,7 +2296,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base), soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base),
OMAP2_SRAM_BASE, s->sram_size); OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19), s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
qdev_get_gpio_in(s->ih[0], qdev_get_gpio_in(s->ih[0],
OMAP_INT_24XX_UART1_IRQ), OMAP_INT_24XX_UART1_IRQ),
omap_findclk(s, "uart1_fclk"), omap_findclk(s, "uart1_fclk"),
@ -2304,7 +2305,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
s->drq[OMAP24XX_DMA_UART1_RX], s->drq[OMAP24XX_DMA_UART1_RX],
"uart1", "uart1",
serial_hds[0]); serial_hds[0]);
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
qdev_get_gpio_in(s->ih[0], qdev_get_gpio_in(s->ih[0],
OMAP_INT_24XX_UART2_IRQ), OMAP_INT_24XX_UART2_IRQ),
omap_findclk(s, "uart2_fclk"), omap_findclk(s, "uart2_fclk"),
@ -2313,7 +2314,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
s->drq[OMAP24XX_DMA_UART2_RX], s->drq[OMAP24XX_DMA_UART2_RX],
"uart2", "uart2",
serial_hds[0] ? serial_hds[1] : NULL); serial_hds[0] ? serial_hds[1] : NULL);
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
qdev_get_gpio_in(s->ih[0], qdev_get_gpio_in(s->ih[0],
OMAP_INT_24XX_UART3_IRQ), OMAP_INT_24XX_UART3_IRQ),
omap_findclk(s, "uart3_fclk"), omap_findclk(s, "uart3_fclk"),

41
hw/omap_uart.c
View File

@ -26,6 +26,7 @@
/* UARTs */ /* UARTs */
struct omap_uart_s { struct omap_uart_s {
MemoryRegion iomem;
target_phys_addr_t base; target_phys_addr_t base;
SerialState *serial; /* TODO */ SerialState *serial; /* TODO */
struct omap_target_agent_s *ta; struct omap_target_agent_s *ta;
@ -68,11 +69,15 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
return s; return s;
} }
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_uart_s *s = (struct omap_uart_s *) opaque; struct omap_uart_s *s = (struct omap_uart_s *) opaque;
addr &= 0xff; if (size == 4) {
return omap_badwidth_read8(opaque, addr);
}
switch (addr) { switch (addr) {
case 0x20: /* MDR1 */ case 0x20: /* MDR1 */
return s->mdr[0]; return s->mdr[0];
@ -103,11 +108,14 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_uart_write(void *opaque, target_phys_addr_t addr, static void omap_uart_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_uart_s *s = (struct omap_uart_s *) opaque; struct omap_uart_s *s = (struct omap_uart_s *) opaque;
addr &= 0xff; if (size == 4) {
return omap_badwidth_write8(opaque, addr, value);
}
switch (addr) { switch (addr) {
case 0x20: /* MDR1 */ case 0x20: /* MDR1 */
s->mdr[0] = value & 0x7f; s->mdr[0] = value & 0x7f;
@ -145,32 +153,27 @@ static void omap_uart_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap_uart_readfn[] = { static const MemoryRegionOps omap_uart_ops = {
omap_uart_read, .read = omap_uart_read,
omap_uart_read, .write = omap_uart_write,
omap_badwidth_read8, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUWriteMemoryFunc * const omap_uart_writefn[] = { struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
omap_uart_write, struct omap_target_agent_s *ta,
omap_uart_write,
omap_badwidth_write8,
};
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk, qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr) const char *label, CharDriverState *chr)
{ {
target_phys_addr_t base = omap_l4_attach(ta, 0, 0); target_phys_addr_t base = omap_l4_attach_region(ta, 0, NULL);
struct omap_uart_s *s = omap_uart_init(base, irq, struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr); fclk, iclk, txdma, rxdma, label, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN); memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap.uart", 0x100);
s->ta = ta; s->ta = ta;
cpu_register_physical_memory(base + 0x20, 0x100, iomemtype); memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
return s; return s;
} }