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hw/char: Remove omap2_uart
Remove the OMAP2 specific code from omap_uart.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903160751.4100218-40-peter.maydell@linaro.org
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@ -28,7 +28,6 @@ struct omap_uart_s {
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MemoryRegion iomem;
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hwaddr base;
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SerialMM *serial; /* TODO */
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struct omap_target_agent_s *ta;
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omap_clk fclk;
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qemu_irq irq;
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@ -36,8 +35,6 @@ struct omap_uart_s {
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uint8_t syscontrol;
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uint8_t wkup;
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uint8_t cfps;
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uint8_t mdr[2];
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uint8_t scr;
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uint8_t clksel;
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};
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@ -66,113 +63,3 @@ struct omap_uart_s *omap_uart_init(hwaddr base,
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DEVICE_NATIVE_ENDIAN);
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return s;
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}
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static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
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{
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struct omap_uart_s *s = opaque;
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if (size == 4) {
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return omap_badwidth_read8(opaque, addr);
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}
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switch (addr) {
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case 0x20: /* MDR1 */
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return s->mdr[0];
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case 0x24: /* MDR2 */
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return s->mdr[1];
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case 0x40: /* SCR */
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return s->scr;
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case 0x44: /* SSR */
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return 0x0;
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case 0x48: /* EBLR (OMAP2) */
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return s->eblr;
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case 0x4C: /* OSC_12M_SEL (OMAP1) */
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return s->clksel;
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case 0x50: /* MVR */
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return 0x30;
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case 0x54: /* SYSC (OMAP2) */
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return s->syscontrol;
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case 0x58: /* SYSS (OMAP2) */
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return 1;
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case 0x5c: /* WER (OMAP2) */
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return s->wkup;
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case 0x60: /* CFPS (OMAP2) */
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return s->cfps;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_uart_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_uart_s *s = opaque;
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if (size == 4) {
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omap_badwidth_write8(opaque, addr, value);
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return;
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}
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switch (addr) {
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case 0x20: /* MDR1 */
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s->mdr[0] = value & 0x7f;
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break;
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case 0x24: /* MDR2 */
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s->mdr[1] = value & 0xff;
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break;
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case 0x40: /* SCR */
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s->scr = value & 0xff;
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break;
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case 0x48: /* EBLR (OMAP2) */
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s->eblr = value & 0xff;
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break;
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case 0x4C: /* OSC_12M_SEL (OMAP1) */
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s->clksel = value & 1;
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break;
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case 0x44: /* SSR */
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case 0x50: /* MVR */
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case 0x58: /* SYSS (OMAP2) */
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OMAP_RO_REG(addr);
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break;
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case 0x54: /* SYSC (OMAP2) */
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s->syscontrol = value & 0x1d;
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if (value & 2) {
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omap_uart_reset(s);
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}
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break;
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case 0x5c: /* WER (OMAP2) */
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s->wkup = value & 0x7f;
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break;
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case 0x60: /* CFPS (OMAP2) */
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s->cfps = value & 0xff;
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break;
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default:
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OMAP_BAD_REG(addr);
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}
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}
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static const MemoryRegionOps omap_uart_ops = {
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.read = omap_uart_read,
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.write = omap_uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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struct omap_target_agent_s *ta,
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qemu_irq irq, omap_clk fclk, omap_clk iclk,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, Chardev *chr)
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{
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hwaddr base = omap_l4_attach(ta, 0, NULL);
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struct omap_uart_s *s = omap_uart_init(base, irq,
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fclk, iclk, txdma, rxdma, label, chr);
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memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s, "omap.uart", 0x100);
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s->ta = ta;
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memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
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return s;
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}
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@ -709,11 +709,6 @@ struct omap_uart_s *omap_uart_init(hwaddr base,
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qemu_irq irq, omap_clk fclk, omap_clk iclk,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, Chardev *chr);
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struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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struct omap_target_agent_s *ta,
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qemu_irq irq, omap_clk fclk, omap_clk iclk,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, Chardev *chr);
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void omap_uart_reset(struct omap_uart_s *s);
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struct omap_mpuio_s;
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