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riscv: Separate FPU register size from core register size in gdbstub [v2] 

The size of the FPU registers is dictated by the 'f' and 'd' features,
not the core processor register size. Processors with the 'd' feature
have 64-bit FPU registers. Processors without the 'd' feature but with
the 'f' feature have 32-bit FPU registers.

Signed-off-by: Keith Packard <keithp@keithp.com>
[Palmer: This requires manually triggering a rebuild of
riscv32-softmmu/gdbstub-xml.c]
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Keith Packard 2020-01-28 15:32:16 -08:00 committed by Palmer Dabbelt
parent 0e404da007
commit ae4a70c071
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
2 changed files with 13 additions and 11 deletions
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4
configure vendored
View File

@ -7736,13 +7736,13 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv TARGET_ABI_DIR=riscv
mttcg=yes mttcg=yes
gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml"
;; ;;
riscv64) riscv64)
TARGET_BASE_ARCH=riscv TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv TARGET_ABI_DIR=riscv
mttcg=yes mttcg=yes
gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
;; ;;
sh4|sh4eb) sh4|sh4eb)
TARGET_ARCH=sh4 TARGET_ARCH=sh4

20
target/riscv/gdbstub.c
View File

@ -303,7 +303,12 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{ {
if (n < 32) { if (n < 32) {
return gdb_get_reg64(mem_buf, env->fpr[n]); if (env->misa & RVD) {
return gdb_get_reg64(mem_buf, env->fpr[n]);
}
if (env->misa & RVF) {
return gdb_get_reg32(mem_buf, env->fpr[n]);
}
/* there is hole between ft11 and fflags in fpu.xml */ /* there is hole between ft11 and fflags in fpu.xml */
} else if (n < 36 && n > 32) { } else if (n < 36 && n > 32) {
target_ulong val = 0; target_ulong val = 0;
@ -403,23 +408,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{ {
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32) if (env->misa & RVD) {
if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-64bit-fpu.xml", 0);
} else if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0); 36, "riscv-32bit-fpu.xml", 0);
} }
#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-32bit-csr.xml", 0); 240, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0); 1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64) #elif defined(TARGET_RISCV64)
if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-64bit-fpu.xml", 0);
}
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-64bit-csr.xml", 0); 240, "riscv-64bit-csr.xml", 0);