mirror of https://github.com/xemu-project/xemu.git
hw/arm/musca: Add PPCs
Many of the devices on the Musca board live behind TrustZone Peripheral Protection Controllers (PPCs); add models of the PPCs, using a similar scheme to the MPS2 board models. This commit wires up the PPCs with "unimplemented device" stubs behind them in the correct places in the address map. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
8f69a4c15d
commit
ae3bc71401
289
hw/arm/musca.c
289
hw/arm/musca.c
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@ -27,8 +27,11 @@
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#include "hw/arm/armsse.h"
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#include "hw/boards.h"
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#include "hw/core/split-irq.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/misc/unimp.h"
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#define MUSCA_NUMIRQ_MAX 96
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#define MUSCA_PPC_MAX 3
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typedef enum MuscaType {
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MUSCA_A,
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@ -48,6 +51,24 @@ typedef struct {
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ARMSSE sse;
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SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX];
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SplitIRQ sec_resp_splitter;
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TZPPC ppc[MUSCA_PPC_MAX];
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MemoryRegion container;
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UnimplementedDeviceState eflash[2];
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UnimplementedDeviceState qspi;
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UnimplementedDeviceState mpc[5];
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UnimplementedDeviceState mhu[2];
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UnimplementedDeviceState pwm[3];
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UnimplementedDeviceState i2s;
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UnimplementedDeviceState uart[2];
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UnimplementedDeviceState i2c[2];
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UnimplementedDeviceState spi;
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UnimplementedDeviceState scc;
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UnimplementedDeviceState timer;
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UnimplementedDeviceState rtc;
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UnimplementedDeviceState pvt;
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UnimplementedDeviceState sdio;
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UnimplementedDeviceState gpio;
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} MuscaMachineState;
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#define TYPE_MUSCA_MACHINE "musca"
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@ -68,6 +89,94 @@ typedef struct {
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*/
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#define SYSCLK_FRQ 40000000
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/*
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* Most of the devices in the Musca board sit behind Peripheral Protection
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* Controllers. These data structures define the layout of which devices
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* sit behind which PPCs.
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* The devfn for each port is a function which creates, configures
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* and initializes the device, returning the MemoryRegion which
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* needs to be plugged into the downstream end of the PPC port.
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*/
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typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size);
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typedef struct PPCPortInfo {
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const char *name;
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MakeDevFn *devfn;
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void *opaque;
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hwaddr addr;
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hwaddr size;
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} PPCPortInfo;
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typedef struct PPCInfo {
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const char *name;
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PPCPortInfo ports[TZ_NUM_PORTS];
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} PPCInfo;
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static MemoryRegion *make_unimp_dev(MuscaMachineState *mms,
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void *opaque, const char *name, hwaddr size)
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{
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/*
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* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
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* and return a pointer to its MemoryRegion.
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*/
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UnimplementedDeviceState *uds = opaque;
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sysbus_init_child_obj(OBJECT(mms), name, uds,
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sizeof(UnimplementedDeviceState),
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TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(DEVICE(uds), "name", name);
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qdev_prop_set_uint64(DEVICE(uds), "size", size);
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object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
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}
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static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size)
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{
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/*
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* Create the container MemoryRegion for all the devices that live
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* behind the Musca-A PPC's single port. These devices don't have a PPC
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* port each, but we use the PPCPortInfo struct as a convenient way
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* to describe them. Note that addresses here are relative to the base
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* address of the PPC port region: 0x40100000, and devices appear both
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* at the 0x4... NS region and the 0x5... S region.
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*/
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int i;
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MemoryRegion *container = &mms->container;
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const PPCPortInfo devices[] = {
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{ "uart0", make_unimp_dev, &mms->uart[0], 0x1000, 0x1000 },
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{ "uart1", make_unimp_dev, &mms->uart[1], 0x2000, 0x1000 },
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{ "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 },
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{ "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 },
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{ "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 },
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{ "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 },
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{ "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 },
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{ "rtc", make_unimp_dev, &mms->rtc, 0x8000, 0x1000 },
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{ "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 },
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{ "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 },
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{ "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 },
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{ "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 },
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{ "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 },
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{ "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 },
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{ "mpc0", make_unimp_dev, &mms->mpc[0], 0x12000, 0x1000 },
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{ "mpc1", make_unimp_dev, &mms->mpc[1], 0x13000, 0x1000 },
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};
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memory_region_init(container, OBJECT(mms), "musca-device-container", size);
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for (i = 0; i < ARRAY_SIZE(devices); i++) {
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const PPCPortInfo *pinfo = &devices[i];
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MemoryRegion *mr;
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mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
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memory_region_add_subregion(container, pinfo->addr, mr);
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}
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return &mms->container;
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}
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static void musca_init(MachineState *machine)
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{
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MuscaMachineState *mms = MUSCA_MACHINE(machine);
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@ -75,6 +184,9 @@ static void musca_init(MachineState *machine)
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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MemoryRegion *system_memory = get_system_memory();
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DeviceState *ssedev;
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DeviceState *dev_splitter;
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const PPCInfo *ppcs;
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int num_ppcs;
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int i;
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assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX);
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@ -121,6 +233,183 @@ static void musca_init(MachineState *machine)
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"EXP_CPU1_IRQ", i));
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}
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/*
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* The sec_resp_cfg output from the SSE-200 must be split into multiple
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* lines, one for each of the PPCs we create here.
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*/
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object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
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TYPE_SPLIT_IRQ);
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object_property_add_child(OBJECT(machine), "sec-resp-splitter",
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OBJECT(&mms->sec_resp_splitter), &error_fatal);
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object_property_set_int(OBJECT(&mms->sec_resp_splitter),
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ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal);
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object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
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"realized", &error_fatal);
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dev_splitter = DEVICE(&mms->sec_resp_splitter);
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qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0,
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qdev_get_gpio_in(dev_splitter, 0));
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/*
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* Most of the devices in the board are behind Peripheral Protection
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* Controllers. The required order for initializing things is:
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* + initialize the PPC
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* + initialize, configure and realize downstream devices
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* + connect downstream device MemoryRegions to the PPC
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* + realize the PPC
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* + map the PPC's MemoryRegions to the places in the address map
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* where the downstream devices should appear
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* + wire up the PPC's control lines to the SSE object
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*
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* The PPC mapping differs for the -A and -B1 variants; the -A version
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* is much simpler, using only a single port of a single PPC and putting
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* all the devices behind that.
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*/
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const PPCInfo a_ppcs[] = { {
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.name = "ahb_ppcexp0",
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.ports = {
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{ "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100000 },
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},
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},
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};
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/*
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* Devices listed with an 0x4.. address appear in both the NS 0x4.. region
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* and the 0x5.. S region. Devices listed with an 0x5.. address appear
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* only in the S region.
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*/
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const PPCInfo b1_ppcs[] = { {
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.name = "apb_ppcexp0",
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.ports = {
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{ "eflash0", make_unimp_dev, &mms->eflash[0],
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0x52400000, 0x1000 },
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{ "eflash1", make_unimp_dev, &mms->eflash[1],
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0x52500000, 0x1000 },
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{ "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000 },
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{ "mpc0", make_unimp_dev, &mms->mpc[0], 0x52000000, 0x1000 },
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{ "mpc1", make_unimp_dev, &mms->mpc[1], 0x52100000, 0x1000 },
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{ "mpc2", make_unimp_dev, &mms->mpc[2], 0x52200000, 0x1000 },
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{ "mpc3", make_unimp_dev, &mms->mpc[3], 0x52300000, 0x1000 },
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{ "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 },
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{ "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 },
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{ }, /* port 9: unused */
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{ }, /* port 10: unused */
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{ }, /* port 11: unused */
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{ }, /* port 12: unused */
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{ }, /* port 13: unused */
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{ "mpc4", make_unimp_dev, &mms->mpc[4], 0x52e00000, 0x1000 },
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},
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}, {
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.name = "apb_ppcexp1",
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.ports = {
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{ "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 },
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{ "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 },
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{ "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 },
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{ "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 },
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{ "uart0", make_unimp_dev, &mms->uart[0], 0x40105000, 0x1000 },
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{ "uart1", make_unimp_dev, &mms->uart[1], 0x40106000, 0x1000 },
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{ "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 },
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{ "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 },
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{ "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 },
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{ "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 },
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{ "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000 },
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{ "rtc", make_unimp_dev, &mms->rtc, 0x4010d000, 0x1000 },
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{ "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 },
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{ "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 },
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},
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}, {
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.name = "ahb_ppcexp0",
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.ports = {
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{ }, /* port 0: unused */
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{ "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 },
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},
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},
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};
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switch (mmc->type) {
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case MUSCA_A:
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ppcs = a_ppcs;
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num_ppcs = ARRAY_SIZE(a_ppcs);
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break;
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case MUSCA_B1:
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ppcs = b1_ppcs;
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num_ppcs = ARRAY_SIZE(b1_ppcs);
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break;
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default:
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g_assert_not_reached();
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}
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assert(num_ppcs <= MUSCA_PPC_MAX);
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for (i = 0; i < num_ppcs; i++) {
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const PPCInfo *ppcinfo = &ppcs[i];
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TZPPC *ppc = &mms->ppc[i];
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DeviceState *ppcdev;
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int port;
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char *gpioname;
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sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
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sizeof(TZPPC), TYPE_TZ_PPC);
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ppcdev = DEVICE(ppc);
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for (port = 0; port < TZ_NUM_PORTS; port++) {
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const PPCPortInfo *pinfo = &ppcinfo->ports[port];
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MemoryRegion *mr;
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char *portname;
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if (!pinfo->devfn) {
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continue;
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}
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mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
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portname = g_strdup_printf("port[%d]", port);
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object_property_set_link(OBJECT(ppc), OBJECT(mr),
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portname, &error_fatal);
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g_free(portname);
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}
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object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
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for (port = 0; port < TZ_NUM_PORTS; port++) {
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const PPCPortInfo *pinfo = &ppcinfo->ports[port];
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if (!pinfo->devfn) {
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continue;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
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gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
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qdev_connect_gpio_out_named(ssedev, gpioname, port,
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qdev_get_gpio_in_named(ppcdev,
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"cfg_nonsec",
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port));
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
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qdev_connect_gpio_out_named(ssedev, gpioname, port,
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qdev_get_gpio_in_named(ppcdev,
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"cfg_ap", port));
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g_free(gpioname);
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}
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gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
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qdev_connect_gpio_out_named(ssedev, gpioname, 0,
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qdev_get_gpio_in_named(ppcdev,
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"irq_enable", 0));
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
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qdev_connect_gpio_out_named(ssedev, gpioname, 0,
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qdev_get_gpio_in_named(ppcdev,
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"irq_clear", 0));
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
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qdev_connect_gpio_out_named(ppcdev, "irq", 0,
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qdev_get_gpio_in_named(ssedev,
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gpioname, 0));
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g_free(gpioname);
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qdev_connect_gpio_out(dev_splitter, i,
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qdev_get_gpio_in_named(ppcdev,
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"cfg_sec_resp", 0));
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}
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armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x2000000);
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}
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